QN8027芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

QN8027

High Performance Digital FM Transmitter for Portable Devices

________ General Description ________ ___________ Key Features __________

• Worldwide FM Band Transmit

The QN8027 is a high performance, low power, full-

featured single-chip stereo FM transmitter designed for

portable audio/video players, automotive accessories, cell

phones, and GPS personal navigation devices. The

QN8027 covers frequencies from 76 MHz to 108 MHz in

50/100/200 kHz step sizes for worldwide FM band support.

The QN8027 also supports RDS/RBDS data transmit.

• 76 MHz to 108 MHz full band tuning in

50/100/200 kHz step sizes

• 50/75μs pre-emphasis

• Ease of Integration

• Small footprint, 3 x 3 x 0.95mm MSOP10

• Only 2 external passive components required

• Adaptive antenna tuning

• Low cellular and GPS band spurs

• High Immunity to TDMA (GSM/GPRS) burst noise

• Multiple crystal frequencies supported

• I²C interface

The QN8027 integrates a complete transmitter function,

from stereo audio input to RF antenna port, for worldwide

FM band personal area broadcasting. It includes variable

input gain programming, selectable pre-emphasis, precision

low-spur MPX stereo encoding and pilot tone generation,

low-noise PLL-based modulation, and an on-chip power

amplifier with variable output level and RF band-pass

filtering to ensure optimum transmit spectrum purity.

• Low Power Consumption

• 7.0 mA of FCC output level

An integrated crystal oscillator and on-chip digital

calibration circuits eliminate external tuning components

and enable tuning-free manufacturing. Support for

12/24MHz reference clocks allows the chip to use readily

available system clocks. Integrated saturation detection and

a programmable audio interface eliminate distortion,

optimize audio fidelity, and support a wide range of input

audio levels. A low power IDLE mode extends battery life.

An integrated LDO enables direct connection to the battery

and provides high PSRR for superior noise suppression, in

particular TDMA noise from GSM/GPRS phones.

• Integrated voltage regulator, direct connect to battery

• Power saving IDLE mode

• High Performance FM Transmitter (FMT)

• 65dB Stereo SNR, 0.04% THD

• Maximum 119 dBuVp RF output level with 42dB

adjustable range

• Automatic Input Audio Sensing

• RF power automatically turned off if no input

audio signal for 60s

The QN8027’s small footprint, high integration with

minimum external component count, and support for

12/24MHz clock frequencies make it easy to integrate into

• RDS/RBDS Transmit

• Supports US and European data service,

a

variety of small form-factor low-power portable

including TMC (Traffic Messaging Channel)

applications. Integrated low-phase noise digital

synthesizers and extensive on-chip auto calibration ensures

robust consistent performance over temperature and

process variations. An integrated voltage regulator enables

direct connection to a battery and provides high PSRR for

superior noise suppression. A low-power IDLE mode

extends battery life.

• Robust Operation

• -25⁰C to +85⁰C operation

• ESD protection on all input and output pads

ESD protection is on all pins. The QN8027 is fabricated in

highly reliable CMOS technology.

_____________________________ Typical Applications __________________________

Cell Phones / PDAs / Smart Phones

Portable Audio & Media Players

GPS Personal Navigation Devices

Automotive and Accessories

Rev 1.1 (04/10)

Page 1

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

CONTENTS

1

2

3

4

Functional Block Diagram ..............................................................................................................................3

Pin Assignments ..............................................................................................................................................3

Electrical Specifications ..................................................................................................................................3

Functional Description ....................................................................................................................................3

4.1 Transmit Mode..........................................................................................................................3

4.2 Idle Mode..................................................................................................................................3

4.3 Audio Interface .........................................................................................................................3

4.4 Audio Processing......................................................................................................................3

4.5 Channel Setting.........................................................................................................................3

4.6 RDS/RBDS...............................................................................................................................3

5

Control Interface Protocol...............................................................................................................................3

5.1 I²C Serial Control Interface ......................................................................................................3

6

7

8

User Control Registers.....................................................................................................................................3

Package Description ........................................................................................................................................3

Solder Reflow Profile......................................................................................................................................3

8.1 Package Peak Reflow Temperature ..........................................................................................3

8.2 Classification Reflow Profiles ..................................................................................................3

8.3 Maximum Reflow Times ..........................................................................................................3

Rev 1.1 (04/10)

Page 2

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

REVISION HISTORY

REVISION

CHANGE DESCRIPTION

DATE

0.1

Datasheet draft.

12/08/08

Check the grammar and syntax, Update the data ,the key features, and user control

registers, Delete the Section 4.6 Audio Encryption for Privacy , Modify the Vcc

value ;modify the pin FMO back RFO;

0.21

02/23/09

0.22

0.23

0.24

0.25

Modify Table 6: match the notes with the parameters; add “at maximal power”

03/18/09

03/19/09

03/27/09

04/08/09

Add Ordering Information

Modify Figure 11: save to slave; and I²C slave address

Modify register 07h [2:0] and the description of the register 10h [6:0] about PA

1. Add section 4.7 Power Setting;

2. Modify reg 00h Bit 7: wo → r/w;

3. Delete reg 02h [7]: ‘and de-emphasis’;

4. Modify reg 03h [7:6]: internal oscillator → crystal: [5:0] add ‘when use crystal on

XTAL1/XTAL2’.

0.26

04/08/09

5. Modify reg 11h:FEDV→FDEV

6. Modify reg 12h [7] No RDS →RDS disable;

05/25/09

06/17/09

01/16/10

03/17/10

04/13/10

0.27

0.28

0.29

1.0

Modify Vcc MAX: 4.2V J 5.0V

Modify the description of Reg 07h [2:0]

Update the data in Chapter 3.

Modify Reg06h[3:0] 0000Æ0100

Update the I_TXvalue in Table 4

1.1

STATEMENT:

Users are responsible for compliance with local regulatory requirements for low power unlicensed FM

broadcast operation. Quintic is not responsible for any violations resulting from user’s intentional or

unintentional breach of regulatory requirements in personal or commercial use.

Rev 1.1 (04/10)

Page 3

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

1 FUNCTIONAL BLOCK DIAGRAM

Figure 1: QN8027-SANC Functional Blocks

Rev 1.1 (04/10)

Page 4

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

2 PIN ASSIGNMENTS

XTAL2

XTAL1

VCC

1

2

3

4

5

10

9

ALI

ARI

VIO

SDA

SCL

8

GND

7

RFO

6

(Top View)

Figure 2: QN8027 Device Pin Out

Table 1: Pin Descriptions

PINS

NAME

DESCRIPTION

On-chip crystal driver port 2.

If using an external clock source, connect this pin to ground.

1

XTAL2

On-chip crystal driver port 1.

If using an external clock source, connect this pin to inject the clock.

Voltage supply

2

XTAL1

3

4

VCC

GND

RFO

SCL

SDA

VIO

ARI

Ground

5

Transmitter RF output – connect to matched antenna.

Clock for I²C serial bus.

Bi-directional data line for I²C serial bus.

IO voltage – specifies voltage limit for all digital pins.

Analog audio input – right channel

Analog audio input – left channel

6

7

8

9

10

ALI

Rev 1.1 (04/10)

Page 5

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

3 ELECTRICAL SPECIFICATIONS

Table 2: Absolute Maximum Ratings

SYMBOL

PARAMETER

Supply voltage

CONDITIONS

VCC to GND

SCL, SDA to GND

MIN

-0.3

-55

MAX

5

UNIT

V

V_bat

V_IO

T_s

Logic signals

3.6

V

Storage temperature

+150

^oC

Table 3: Recommended Operating Conditions

SYMBOL

Vcc

PARAMETER

Supply voltage

CONDITIONS

VCC to GND

MIN

TYP

MAX

UNIT

V

2.7

-25

3.3

5.0

+85

1400

3.6

T_A

Operating temperature

^oC

L/R channel input

signal level

Single ended peak to

peak voltage

V_ain

1000

mV

V

V_IO

Digital I/O voltage

1.6

Rev 1.1 (04/10)

Page 6

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Table 4: DC Characteristics

(Vcc = 2.7 ~ 5.0 V, T_A= -25 ~ 85 ^oC, unless otherwise noticed. Typical values are at Vcc = 3.3.V, f carrier=88 MHz and T_A= 25^oC).

SYMBOL

I_TX

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

mA

Transmit mode supply current

Idle mode supply current

7.0¹

13.8²

I_IDLE

Idle mode

1.2

mA

Interface

V_OH

V_OL

V_IH

High level output voltage

Low level output voltage

High level input voltage

Low level input voltage

0.9*V_IO

0.7*V_IO

V

0.1*V_IO

0.4

V_IL

Notes:

1. RFO output at Min level.

2. RFO output at Max level.

Table 5: AC Characteristics

(Vcc = 2.7 ~ 5.0 V, T_A= -25 ~ 85 ^oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and T_A= 25^oC).

SYMBOL

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNIT

Crystal or Clock

frequency

1

F_xtal

12 or 24

MHz

ppm

Crystal frequency

accuracy

2

F_{xtal_err}

Over temperature, and aging

-20

20

Notes:

1. See also XSEL, R04[7].

2. Required by FCC standard.

Rev 1.1 (04/10)

Page 7

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Table 6: Transmitter Characteristics

(Vcc = 2.7 ~ 5.0 V, T_A= -25 ~ 85 ^oC, unless otherwise noticed. Typical values are at Vcc = 3.3V, f carrier=88 MHz and T_A= 25^oC).

SYMBOL

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNIT

R_{audio_in}

C_{audio_in}

G_{audio_In}

ΔG_{audio_In}

Audio input impedance¹

Audio input capacitance¹

Audio input gain

At pin ALI and ARI

RIN[1:0] = 10

5

40

5

kΩ

pF

2

-9

6

dB

Audio gain step

For any gain setting

PETC = 1

0.5

1

1.5

78.7

52.5

71.3

47.5

75

50

64

Pre-emphasis time constant¹

τ_emph

μs

PETC = 0

MONO, Δf = 22.5 kHz

SNR_{audio_tx}

Tx audio SNR^{1, 2}

dB

STEREO, Δf = 67.5 kHz,

Δf_pilot= 6.75 kHz

65

0.04

42

0.1

MONO, Δf = 75 kHz

THD_{audio_tx}

Tx audio THD^{1, 2}

%

STEREO, Δf = 67.5 kHz,

Δf_pilot= 6.75 kHz

L/R separation ²

35

dB

α_{LR_tx}

L and R channel gain

imbalance at 1 kHz offset

from DC

B_{LR_tx}

L/R channel imbalance ¹

1

M_pilot

19 kHz pilot modulation ^{2, 5}

Relative to 75 kHz deviation

7

9.0

15

%

SUP_sub

38 kHz sub-carrier ²suppression

70

dB

Output capacitance tuning

range¹

C_tune

P_out

5

30

pF

RF Channel frequency =

88 MHz

RF output voltage swing³

82

119

dBμV

Power gain step

Over process, temperature

Over 76 MHz ~ 108 MHz

120 kHz to 240 kHz offset

240 kHz to 600 kHz offset

>600 kHz offset

0.75

dB

ΔG_{RF_Out}

ΔP_out

Power gain flatness

-2

2

-50

-45

-40

108

200

P_mask

RF output spectrum mask⁴

dBc

F_rf

RF channel frequency

Channel frequency step

76

50

MHz

kHz

F_ch

100

75

Channel center frequency

accuracy⁶

Pilot Tone frequency accuracy^1,6

F_err

F_perr

-2

2

kHz

Hz

Modulation peak frequency

deviation

F_pk

kHz

Notes:

Rev 1.1 (04/10)

Page 8

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

SYMBOL

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNIT

1. Guaranteed by design.

2. 1000mVp-p, 1 kHz tone at ALI pin, no input signal at ARI pin.

3. Into matched antenna (see application note for details).

4. Within operating band 76 MHz to 108 MHz.

5. Value set with GAIN_TXPLT[3:0] (reg. 02h, bits 3:0). The user must conform to local regulatory requirements

for low-power unlicensed FM broadcast operation when setting this value.

6. Required by FCC standard.

Table 7: Timing Characteristics

(Vcc = 2.7 ~ 5.0 V, T_A= -25 ~ 85 ^oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and T_A= 25^oC).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

From rising edge of Power-On

to PLL settled and transmitter

ready for transmission.

Chip power-up time ¹

0.1

Sec

τ_pup

Channel switching

time¹

From any channel to any

channel.

10

ms

τ_chsw

Notes:

1. Guaranteed by design.

Rev 1.1 (04/10)

Page 9

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Table 8: I²C Interface Timing Characteristics

(Vcc = 2.7 ~ 5.0 V, T_A= -25 ~ 85 ^oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and T_A= 25^oC).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

f_SCL

t_LOW

t_HI

I²C clock frequency

Clock Low time

Clock High time

400

kHz

μs

1.3

0.8

μs

SCL input to SDA

falling edge start ^1,3

t_ST

0.6

μs

SDA falling edge to

t_STHD

SCL falling edge start³

t_rc

t_fc

SCL rising edge³

SCL falling edge³

Level from 30% to 70%

Level from 70% to 30%

300

ns

SCL falling edge to

t_dtHD

t_dtc

t_stp

t_w

20

ns

next SDA rising edge³

SDA rising edge to

900

next SCL rising edge³

SCL rising edge to

SDA rising edge ^2,3

Duration before restart³

0.6

1.3

μs

pF

SCL, SDA capacitive

loading³

C_b

10

Notes:

1. Start signaling of I²C interface.

2. Stop signaling of I²C interface.

3. Guaranteed by design.

Figure 3: I²C Serial Control Interface Timing Diagram

Rev 1.1 (04/10)

Page 10

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

4 FUNCTIONAL DESCRIPTION

The QN8027 is a high performance low power single chip FM transmitter IC that supports worldwide FM broadcast band

operation. It has an IDLE mode for saving power. RDS/RBDS data service is also supported.

4.1 Transmit Mode

The QN8027 transmitter uses a highly digitized architecture. The input left and right analog audio signals are first

adjusted by VGA, and then digitized by two high resolution ADCs into the digital domain. Pre-emphasis and MPX

encoding are then performed. If RDS mode is enabled, the RDS signal will also be mixed with the MPX signal and the

combined output will be fed into a high performance digital FM modulator which generates FM signal at RF carrier

frequency. The FM signal is then filtered and amplified by the PA.

The QN8027 can deliver up to 121dBμV output signal to an external antenna and/or matching network. An RF VGA

provides a 42dB output power control range in 0.75 dB steps and can be programmed through the serial control bus. Output

power control and in-band power flatness can be easily achieved by a calibration circuit. This wide range of control allow

for various antenna configurations such as loop, monopole, or meandering traces on PCB. An integrated RF bandpass filter

ensures optimal output spectrum purity.

4.2 Idle Mode

The QN8027 features a low power IDLE mode for fast turn around and power savings. After power up, the QN8027 will

enter IDLE mode automatically.

4.3 Audio Interface

The QN8027 has a highly flexible analog audio interface. For audio input, the signal is AC coupled with 3dB corner

frequency less than 50Hz. It has 4 different input impedances and 15dB adjustable gain range. Digital gain provides more

accurate gain control (in 1dB steps) to optimize the SNR and linearity. The gain setting can be manually set through the

serial interface.

4.4 Audio Processing

The QN8027 supports audio AGC, programmable pre-emphasis. When there is no audio signal for a pre-determined

period, AGC will power down the transmitter. A peak detector is also integrated to measure the input audio level. User

can program VGA based on the peak value.

Stereo signal is generated by the MPX circuit. It combines the left and right channel signals in the following way:

m(t) =

[

L(t) + R(t)

]

+

[

L(t) − R(t) cos( 4πft + 2θ ₀) + α cos( 2πft + θ ₀) + d (t) cos( 6πft + 3θ ₀)

]

Here, L(t) and R(t) correspond to the audio signals on left and right channels respectively, f = 19 kHz, θ is the initial phase

of pilot tone and α is the magnitude of pilot tone, and d(t) is RDS signal. In mono mode, only the L+R portion of audio

signal is transmitted. The 19 kHz pilot tone is generated by the MPX circuit which contributes 9% of peak modulation,

and RDS signal will contribute 2.1% of peak modulation.

A pre-emphasis function is also integrated with both 75μs and 50μs time constants. The time constant can be programmed

through the serial control interface.

Rev 1.1 (04/10)

Page 11

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

4.5 Channel Setting

By programming channel index CH[9:0], the RF channel can be set to any frequency between 76 MHz ~ 108 MHz in 50

kHz steps. The channel index and RF frequency have the following relationship:

F_RF= (76 + 0.05 x Channel Index), where F_RFis the RF frequency in MHz.

The QN8027 has an integrated crystal oscillator and supports 12/24M Hz crystals. Alternatively, the QN8027 can be

driven externally by clock source.

4.6 RDS/RBDS

The QN8027 supports RDS/RBDS data transmitting, including station ID, Meta data, TMC information, etc. RDS/RBDS

data communicates with an external MCU through the serial control interface.

4.7 Power Setting

Reg 10H[6:0] ‘PPA_TRGT’ is used for PA output power control.

The PA output power expression of the PA output power is:

Power = (0.62×PA_TRGT+71)dBuV

And the PA_TRRGT range is 20~75.

PA output power setting will not efficient immediately, it need to enter IDLE mode and re-enter TX mode, or when the

frequency changed the PA output power setting will take effect.

Rev 1.1 (04/10)

Page 12

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

5 CONTROL INTERFACE PROTOCOL

The QN8027 supports an I²C serial interface. At power-on, all register bits are set to default values.

5.1 I²C Serial Control Interface

The QN8027 uses the Phillips I²C standard in the I²C serial interface.

The I²C (L2) bus is a simple bi-directional bus interface. The bus requires only serial data (SDA) and serial clock (SCL)

signals. The bus is 8-bit oriented. Each device is recognized with a unique address. Each register is also recognized with a

unique address. The L2 bus operates with a maximum frequency of 400 kHz. Each data put on the SDA must be 8 bits

long (Byte) from MSB to LSB and each byte sent should be acknowledged by an “ACK” bit. In case a byte is not

acknowledged, the transmitter should generate a stop condition or restart the transmission. If a stop condition is created

before the whole transmission is completed, the remaining bytes will keep their old setting. In case a byte is not completely

transferred, it will be discarded.

Data transfer to and from the QN8027 can begin when a start condition is created. This is the case if a transition from HIGH

to LOW on the SDA line occurs while the SCL is HIGH. The first byte transferred represents the address of the IC plus the

data direction. The default IC address is 0x2C. A LOW LSB of this byte indicates data transmission (WRITE) while a

HIGH LSB indicates data request (READ). This means that the first byte to be transmitted to the QN8027 should be

“0x58” for a WRITE operation or “0x59” for a READ operation.

The second byte is the starting register address (N) for write/read operation. The following bytes are register data for

address N, N+1, N+2, etc. There is no limit on the number of bytes in each transmission. A transmission can be terminated

by generating a stop condition, which is SDA transition from LOW to HIGH while SCL is HIGH. For write operation,

master stops transmission after the last byte. For read operation, master doesn’t send ACK after receiving the last read back

byte; then stops the transmission.

Rev 1.1 (04/10)

Page 13

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

The timing diagrams below illustrate both write and read operations.

I²C Write Operation

SCL

SDA

A5 A4 A3 A2

Base Address

A0

A7 A6

A1

D7 D6 D5 D4 D3 D2 D1 D0

Data Byte 1

ACK by

Start

I²C slave Address

ACK by

R/W ACK by

QN8027

SCL

SDA

D1

D7 D6 D5 D4 D3 D2 D1 D0

ACK by

D7 D6 D5 D4 D3 D2

Data Byte 3

D0

D7 D6 D5 D4 D3 D2

Data Byte n

D0

D1

ACK by

QN8027

ACK by Stop

QN8027

Data Byte 2

QN8027

I²C Read Operation

SCL

SDA

Start

A5 A4 A3 A2

Base Address

A0

A7 A6

A1

I²C slave Address

ACK by

Stop

ACK by

R/W

QN8027

SCL

SDA

D1

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2

Data Byte n

D0

I²C slave Address

ACK by

Data Byte 1

ACK by

micro

Stop

ACK by

Start

R/W

QN8027

micro

Figure 4: I²C Serial Control Interface Protocol

Notes:

1. The default IC address is 0x2C.

2. “0x58” for a WRITE operation, “0x59” for a READ operation.

Rev 1.1 (04/10)

Page 14

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

6 USER CONTROL REGISTERS

-------- THIS IS A PREVIEW LIST. Number and content of registers subject to change without notice --------

There are 19 user accessible control registers. All registers not listed below are for manufacturing use only.

Table 9: Summary of User Control Registers

REGISTER

NAME

SYSTEM

USER CONTROL FUNCTIONS

Sets device modes, resets.

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

CH1

Lower 8 bits of 10-bit channel index.

Audio controls, gain of TX pilot frequency deviation.

XCLK pin control.

GPLT

REG_XTL

REG_VGA

CID1

TX mode input impedance, crystal frequency setting.

Device ID numbers.

CID2

Device ID numbers.

STATUS

RDSD0

RDSD1

RDSD2

RDSD3

RDSD4

RDSD5

RDSD6

RDSD7

PAC

Device status indicators.

RDS data byte 0.

RDS data byte 1.

RDS data byte 2.

RDS data byte 3.

RDS data byte 4.

RDS data byte 5.

RDS data byte 6.

RDS data byte 7.

PA output power target control.

Specify total TX frequency deviation.

Specify RDS frequency deviation, RDS mode selection.

FDEV

RDS

Rev 1.1 (04/10)

Page 15

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Register Bit R/W Status:

RO - Read Only: You can not program these bits.

WO - Write Only: You can write and read these bits; the value you read back will be the same as written.

R/W - Read/Write: You can write and read these bits; the value you read back can be different from the value written.

Typically, the value is set by the chip itself.

Word: SYSTEM

Address: 00h

Bit 0

(LSB)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

swrst

r/w

recal

wo

txreq

wo

mono

wo

mute

wo

rdsrdy

wo

ch[9]

wo

ch[8]

wo

Bit

Symbol

Default

Description

7

SWRST

0

Reset all registers to default values

0

1

Keep the current value.

Reset to default values.

6

RECAL

0

Reset the state to initial states and recalibrate all blocks.

No reset. FSM runs normally.

0

1

Reset the FSM. After this bit is de-asserted, FSM will go through all the

power up and calibration sequence.

5

4

3

TXREQ

MONO

MUTE

0

Transmission request:

0

1

Stay in IDLE mode.

Enter Transmit mode.

Force MONO mode for transmission:

0

1

Stereo mode.

MONO mode.

Audio Mute enable:

0

1

Not Mute

Mute

2

RDSRDY

CH[9:8]

0

RDS transmitting ready: If user want the chip transmitting all the 8 bytes in

RDS0~RDS7, user should toggle this bit. Then the chip internally will fetch these

bytes after completing transmitting of current group.

1:0

01

Highest 2 bits of 10-bit channel index:

Channel freq is (76+CH*0.05) MHz

Rev 1.1 (04/10)

Page 16

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Word: CH1

Address: 01h

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ch[7]

wo

ch[6]

wo

ch[5]

wo

ch[4]

wo

ch[3]

wo

ch[2]

wo

ch[1]

wo

ch[0]

wo

Bit

Symbol

Default

Description

7:0

CH[7:0]

0000 0000

Lower 8 bits of 10-bit Channel index. Channel used for TX.

Word: GPLT

Address: 02h

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

tc

priv_en

wo

T1m_sel[1]

wo

T1m_sel[0]

wo

gain_txplt[3]

wo

gain_txplt[2]

wo

gain_txplt[1]

wo

gain_txplt[0]

wo

Bit

Symbol

Default

Description

7

TC

1

Pre-emphasis time constant

TC

0

Time constant (us)

50

75

1

6

priv_en

0

Enable the privacy mode (audio scramble and RDS encryption)

priv_en

Privacy mode

disabled

0

1

enabled

5:4

t1m_sel[1:0]

10

Selection of 1 minute time for PA off when no audio.

The real time is (58+t1m_sel) seconds

T1m_sel[1:0]

time

00

01

10

11

58s

59s

60s

Infinity (never)

3:0

GAIN_TXPLT[3:0]

1001

Gain of TX pilot to adjust pilot frequency deviation. Refer to peak

frequency deviation of MPX signal when audio input is full scale.

GAIN_TXPLT[5:0]

value

0111

1000

7% * 75KHz

8% * 75KHz

Rev 1.1 (04/10)

Page 17

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

1001

1010

9% * 75KHz

10% * 75KHz

Word: REG_XTL

Address: 03h

Bit 7

xinj[1]

wo

Bit 6

Bit 5

xisel[5]

wo

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

xisel[0]

wo

xinj[0]

wo

xisel[4]

wo

xisel[3]

wo

xisel[2]

wo

xisel[1]

wo

Bit

7:6

Symbol

Default

Description

XINJ[1:0]

00

Select the reference clock source

XINJ[1:0]

Clock source

00

01

10

11

Use crystal on XTAL1/XTAL2

Inject digital clock from XTAL1

Single end sine-wave injection on XTAL1

Differential sine-wave injection on XTAL1/2

5:0

XISEL[5:0]

010000

Crystal oscillator current control. 6.25uA*XISEL[5:0], 0-400uA when use

crystal on XTAL1/XTAL2.

Word: REG_VGA

Address: 04h

Bit 0

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

rin[0]

wo

xsel

wo

gvga[2]

wo

gvga[1]

wo

gvga[0]

wo

GDB[1]

wo

GDB[0]

wo

rin[1]

wo

Bit

Symbol

Default

Description

7

XSEL

1

Crystal frequency selection

XSEL

XTAL frequency (MHz)

0

1

12

24

6:4

GVGA[2:0]

011

TX input buffer gain (dB)

VGAG[2:0]

RIN[1:0]

00

3

01

-3

0

10

-9

-6

-3

11

000

001

010

-15

-12

-9

6

9

3

Rev 1.1 (04/10)

Page 18

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

011

12

6

0

3

6

-6

-3

0

100

15

9

101

18

12

11X

Reserved

3:2

GDB[1:0]

00

TX digital gain

GDB[1:0]

Digital gain

0 dB

00

01

10

11

1 dB

2 dB

reserved

1:0

RIN[1:0]

10

TX mode input impedance for both L/R channels.

RIN[1:0]

Input impedance (KΩ)

00

01

10

11

5

10

20

40

Word: CID1

Address: 05h (RO)

Bit 7

(MSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

cid2[0]

ro

cid0[2]

ro

cid0[1]

ro

cid0[0]

ro

cid1[2]

ro

cid1[1]

ro

cid1[0]

ro

cid2[1]

ro

Bit

Symbol

Default

Description

7:5

CID0[2:0]

rrr

reserved

Chip ID for product family

4:2

CID1[2:0]

rrr

000

CID1[2:0]

000

Product Family

FM

001-111

reserved

1:0

CID2[1:0]

rr

Chip ID for minor revision

01

CID2[1:0]

Minor revision

00

01

10

11

1

2

3

4

Rev 1.1 (04/10)

Page 19

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Word: CID2

Address: 06h (RO)

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

cid3[3]

ro

cid3[2]

ro

cid3[1]

ro

cid3[0]

ro

cid4[3]

ro

cid4[2]

ro

cid4[1]

ro

cid4[0]

ro

Bit

Symbol

CID3[3:0]

Default

Description

7:4

rrrr

Chip ID for product ID

CID3[2:0]

0100

Product

QN8027

reserved

others

3:0

CID4[3:0]

rrrr

Chip ID for major revision is 1+CID4

0100

CID4[3:0]

0000

Revision number

1

0001

2

0010

3

4

0011

0100-1111

reserved

Word: STATUS

Address: 07h

Bit 0

(LSB)

Bit 7 (MSB)

Bit 6

aud_pk[2]

ro

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

aud_pk[3]

ro

aud_pk[1]

ro

aud_pk[0]

ro

rds_upd

ro

fsm[2]

ro

fsm[1]

ro

fsm[0]

ro

Bit

Symbol

Default

Description

7:4

3

aud_pk[3:0]

RDS_UPD

rrrr

r

Audio peak value at ADC input is aud_pk[3:0]*45mV

RDS TX: To transmit the 8 bytes in RDS0~RDS7, the user should toggle

the register bit RDSRDY. Then the chip internally fetches these bytes

after completing transmitting the current group. Once the chip has

internally fetched these bytes, it will toggle this bit, and the user can write

in another group.

2:0

FSM[2:0]

rrr

Top FSM state code

Rev 1.1 (04/10)

Page 20

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

FSM status

RESET

CALI

FSM[2:0]

000

001

010

IDLE

011

TX_RSTB

100

PA calibration

Transmit

101

110

PA_OFF

111

reserved

Word: RDSD0

Address: 08h

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

rdsd0[4]

wo

Bit 3

rdsd0[3]

wo

Bit 2

Bit 1

rdsd0[7]

wo

rdsd0[6]

wo

rdsd0[5]

wo

rdsd0[2]

wo

rdsd0[1]

wo

rdsd0[0]

wo

Bit

Symbol

RDSD0

Default

Description

7:0

00000000

RDS data byte0 to be sent: Data written into RDSD0~RDSD7 can not be sent

out if user didn’t toggle RDSRDY to allow the data to be loaded into the

internal transmitting buffer.

Word: RDSD1

Address: 09h

Bit 7

(MSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

rdsd1[0]

wo

rdsd1[7]

wo

rdsd1[6]

wo

rdsd1[5]

wo

rdsd1[4]

wo

rdsd1[3]

wo

rdsd1[2]

wo

rdsd1[1]

wo

Bit

Symbol

RDSD1[7:0]

Default

Description

7:0

0000 0000

RDS data byte 1

Rev 1.1 (04/10)

Page 21

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Word: RDSD2

Address: 0Ah

Bit 7

(MSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

rdsd2[0]

wo

rdsd2[7]

wo

rdsd2[6]

wo

rdsd2[5]

wo

rdsd2[4]

wo

rdsd2[3]

wo

rdsd2[2]

wo

rdsd2[1]

wo

Bit

Symbol

RDSD2[7:0]

Default

Description

7:0

0000 0000

RDS data byte 2

Word: RDSD3

Address: 0Bh

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

rdsd3[7]

wo

rdsd3[6]

wo

rdsd3[5]

wo

rdsd3[4]

wo

rdsd3[3]

wo

rdsd3[2]

wo

rdsd3[1]

wo

rdsd3[0]

wo

Bit

Symbol

RDSD3[7:0]

Default

Description

7:0

0000 0000

RDS data byte 3

Word: RDSD4

Address: 0Ch

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

rdsd4[7]

wo

rdsd4[6]

wo

rdsd4[5]

wo

rdsd4[4]

wo

rdsd4[3]

wo

rdsd4[2]

wo

rdsd4[1]

wo

rdsd4[0]

wo

Bit

7:0

Symbol

RDSD4[7:0]

Default

Description

0000 0000

RDS data byte 4

Word: RDSD5

Address: 0Dh

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

rdsd5[7]

wo

rdsd5[6]

wo

rdsd5[5]

wo

rdsd5[4]

wo

rdsd5[3]

wo

rdsd5[2]

wo

rdsd5[1]

wo

rdsd5[0]

wo

Rev 1.1 (04/10)

Page 22

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Bit

Symbol

Default

Description

7:0

RDSD5[7:0]

0000 0000

RDS data byte 5

Word: RDSD6

Address: 0Eh

Bit 7

(MSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

rdsd6[0]

wo

rdsd6[7]

wo

rdsd6[6]

wo

rdsd6[5]

wo

rdsd6[4]

wo

rdsd6[3]

wo

rdsd6[2]

wo

rdsd6[1]

wo

Bit

7:0

Symbol

RDSD6[7:0]

Default

Description

0000 0000

RDS data byte 6

Word: RDSD7

Address: 0Fh

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

rdsd7[7]

wo

rdsd7[6]

wo

rdsd7[5]

wo

rdsd7[4]

wo

rdsd7[3]

wo

rdsd7[2]

wo

rdsd7[1]

wo

rdsd7[0]

wo

Bit

7:0

Symbol

RDSD7[7:0]

Default

Description

0000 0000

RDS data byte 7

Word: PAC

Address: 10h

Bit 0

(LSB)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

txpd_clr

wo

pa_trgt[6]

wo

pa_trgt[5]

wo

pa_trgt[4]

wo

pa_trgt[3]

wo

pa_trgt[2]

wo

pa_trgt[1]

wo

pa_trgt[0]

wo

Bit

Symbol

Default

Description

7

TXPD_CLR

0

TX aud_pk clear signal: Audio peak value is max-hold and stored in

aud_pk[3:0]. Once TXPD_CLR is toggled, the aud_pk value is cleared

and restarted again.

6:0

PA_TRGT[6:0]

111 1111

PA output power target is 0.62*PA_TRGT+71dBu. Valid values are 20-

75.

Rev 1.1 (04/10)

Page 23

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Word: FDEV

Address: 11h

Bit 7

(MSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

tx_fdev[0]

wo

tx_fdev[7]

wo

tx_fdev[6]

wo

tx_fdev[5]

wo

tx_fdev[4]

wo

tx_fdev[3]

wo

tx_fdev[2]

wo

tx_fdev[1]

wo

Bit

Symbol

TX_FDEV[7:0]

Default

Description

7:0

10000001

Specify total TX frequency deviation:

TX frequency deviation = 0.58 kHz*TX_FDEV.

TX_FDEV[7:0]

value

0000 0000 - 1111 1111

0 ~ 255

Word: RDS

Address: 12h

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

rdsen

wo

rdsfdev[6]

wo

rdsfdev[5]

wo

rdsfdev[4]

wo

rdsfdev[3]

wo

rdsfdev[2]

wo

rdsfdev[1]

wo

rdsfdev[0]

wo

Bit

Symbol

RDSEN

Default

Description

7

0

RDS enable:

0

1

RDS disable

RDS enable

6

RDSFDEV[6:0]

000 0110

Specify RDS frequency deviation:

RDS frequency deviation = 0.35KHz*RDSFDEV.

RDSFDEV[6:0]

Value

0~127

000 0000 – 111 1111

Rev 1.1 (04/10)

Page 24

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

7 ORDERING INFORMATION

Part Number

Description

Package

QN8027-SANC

The QN8027 is a high performance, low power, full-featured single-

chip stereo FM transmitter designed for portable audio/video players,

automotive accessories, cell phones, and GPS personal navigation

devices.

3x3 mm Body

[MSOP10]

Rev 1.1 (04/10)

Page 25

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

8 PACKAGE DESCRIPTION

10-Lead plastic package – 3x3 mm Body [MSOP]

Figure 5: MSOP10 Package Outline Dimensions

Millimeters

Symbol

Description

Minimum

0.820

Nominal

Maximum

1.100

A

A1

A2

b

Overall package height

Board standoff

0.95

0.020

-

0.85

0.23

-

0.150

Package thickness

Lead width

0.750

0.950

0.180

0.280

c

Lead thickness

0.090

0.230

D

e

Package’s outside, X-axis

Lead pitch

2.900

3.00

0.50 (BSC)

3.00

4.90

0.60

-

3.100

E

Package’s outside, Y-axis

Lead to lead, Y-axis

Foot length

2.900

4.750

0.400

0°

3.100

5.050

0.800

6°

E1

L

θ

Foot to board angle

Notes:

1. Pin 1 visual index feature may vary, but must be located within the area indicated in the drawing.

2. Dimensioning and tolerance per ASME Y 14.5M.

BSC: Basic Dimension. The theoretically exact value is shown without tolerance.

Rev 1.1 (04/10)

Page 26

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

Carrier Tape Dimensions

Figure 6: MSOP10 Carrier Tape Drawing

NOTES:

1. 10 sprocket hole pitch cumulative tolerance +0.2mm maximum.

2. Camber not to exceed 1mm in 100mm: <1mm/100mm.

3. Pocket position relative to sprocket hole measured

as true position of pocket, not pocket hole.

Rev 1.1 (04/10)

Page 27

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

9 SOLDER REFLOW PROFILE

9.1 Package Peak Reflow Temperature

QN8027 is assembled in a lead-free MSOP package. Since the geometrical size of QN8027 is 3 mm × 3 mm × 0.95 mm, the

volume and thickness is in the category of volume<350 mm³and thickness<1.6 mm in Table 4-2 of IPC/JEDEC J-STD-

020C. The peak reflow temperature is:

T_p= 260^oC

The temperature tolerance is +0^oC and -5^oC. Temperature is measured at the top of the package.

9.2 Classification Reflow Profiles

Profile Feature

Specification*

3°C/second max.

150°C

Average Ramp-Up Rate (tsmax to tP)

Temperature Min (Tsmin)

Pre-heat:

Temperature Max (Tsmax)

Time (ts)

200°C

60-180 seconds

Temperature (T_L)

Time (t_L)

217°C

Time maintained

above:

60-150 seconds

260°C

Peak/Classification Temperature (Tp)

Time within 5°C of Actual Peak Temperature (tp)

20-40 seconds

Ramp-Down Rate

6°C/second max.

8 minutes max.

Time 25°C to Peak Temperature

*Note: All temperatures are measured at the top of the package.

Figure 7: Reflow Temperature Profile

Rev 1.1 (04/10)

Page 28

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

QN8027

9.3 Maximum Reflow Times

All package reliability tests were performed and passed with a pre-condition procedure that repeat a reflow profile, which

conforms to the requirements in Section 9.2, three (3) times.

CONTACT INFORMATION

Quintic Corporation (USA)

Quintic Microelectronics (China)

3211 Scott Blvd., Suite 203

Santa Clara, CA 95054

Tel: +1.408.970.8808

Building 8 B-301A Tsinghua Science Park

1st East Zhongguancun Rd, Haidian

Beijing, China 100084

Fax: +1.408.970.8829

Tel: +86 (10) 8215-1997

Email: support@quinticcorp.com

Web: www.quinticcorp.com

Fax: +86 (10) 8215-1570

Web: www.quinticcorp.com

Rev 1.1 (04/10)

Page 29

Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).

型号:	QN8041AH
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	INTEL CORP
零件包装代码：	LCC
包装说明：	QCCJ, LDCC44,.7SQ
针数：	44
Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01
风险等级：	5.92
具有ADC：	NO
其他特性：	ADDITIONAL SUPPLY VDD = 5V+/-10%
地址总线宽度：
位大小：	8
边界扫描：	NO
CPU系列：	8048
最大时钟频率：	12.5 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：	8
格式：	FIXED POINT
集成缓存：	NO
JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0
长度：	16.5862 mm
低功率模式：	YES
DMA 通道数量：
外部中断装置数量：
I/O 线路数量：	16
串行 I/O 数：
端子数量：	44
计时器数量：	1
片上数据RAM宽度：	8
片上程序ROM宽度：	8
最高工作温度：	70 °C
最低工作温度：
PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
RAM（字节）：	128
RAM（字数）：	128
ROM（单词）：	1000
ROM可编程性：	MROM
座面最大高度：	4.57 mm
速度：	0.833 MHz
子类别：	Microcontrollers
最大压摆率：	115 mA
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	NMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	16.5862 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

电子百科

产品导航

产品型号QN8027的概述

产品型号QN8027的Datasheet PDF文件预览

QN8027相关产品

QN8027相关文章

IC37:专业IC行业平台