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产品型号TPS54229DDAR的概述

芯片TPS54229DDAR的概述 TPS54229DDAR是一款由德州仪器(Texas Instruments,TI)设计和制造的DC-DC降压转换器,广泛应用于电子设备中,尤其是在电源管理领域。该芯片的主要功能是将高电压输入(如12V或更高)转换为低电压输出(如5V、3.3V等),以满足各种数字电路、传感器和微控制器的供电需求。TPS54229DDAR凭借其高效能、易于使用和小型封装,成为设计工程师在电源管理设计中的热门选择。 该芯片采用内部电流模式控制,其高达95%的效率使得功耗损失减小,从而提高了系统的整体效率。此外,TPS54229DDAR支持宽输入电压范围(4.5V至28V),并且具有出色的负载和线性调节能力,使其在稳压应用中表现优异。 芯片TPS54229DDAR的详细参数 1. 输入电压范围:4.5V至28V 2. 输出电压范围:0.8V至20V(可调) 3. 输出电流...

产品型号TPS54229DDAR的Datasheet PDF文件预览

TPS54229  
www.ti.com  
SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
4.5V to 18V INPUT, 2-A SYNCHRONOUS STEP DOWN CONVERTER WITH INTEGRATED  
FET  
Check for Samples: TPS54229  
1
FEATURES  
DESCRIPTION  
The TPS54229 is an adaptive on-time D-CAP2™  
mode synchronous buck converter. TheTPS54229  
enables system designers to complete the suite of  
various end equipment’s power bus regulators with a  
cost effective, low component count, low standby  
current solution. The main control loop for the  
TPS54229 uses the D-CAP2™ mode control which  
provides a fast transient response with no external  
compensation components. The TPS54229 also has  
a proprietary circuit that enables the device to adopt  
to both low equivalent series resistance (ESR) output  
capacitors, such as POSCAP or SP-CAP, and ultra-  
low ESR ceramic capacitors. The device operates  
from 4.5-V to 18-V VIN input. The output voltage can  
be programmed between 0.76 V and 7 V. The device  
also features an adjustable soft start time. The  
TPS54229 is available in the 8-pin DDA package,  
and designed to operate from –40°C to 85°C.  
23  
D-CAP2™ Mode Enables Fast Transient  
Response  
Low Output Ripple and Allows Ceramic Output  
Capacitor  
Wide VIN Input Voltage Range: 4.5 V to 18 V  
Output Voltage Range: 0.76 V to 7.0 V  
Highly Efficient Integrated FETs Optimized  
for Lower Duty Cycle Applications  
– 160 m(High Side) and 110 m(Low Side)  
High Efficiency, Less Than 10 μA at Shutdown  
High Initial Bandgap Reference Accuracy  
Adjustable Soft Start  
Pre-Biased Soft Start  
650-kHz Switching Frequency (fSW  
)
Cycle By Cycle Over Current Limit  
APPLICATIONS  
Wide Range of Applications for Low Voltage  
System  
Digital TV Power Supply  
High Definition Blu-ray Disc™ Players  
Networking Home Terminal  
Digital Set Top Box (STB)  
Vout = 50 mV/div  
TPS54229DDA  
Iout = 1 A/div  
t - Time - 100 ms  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
D-CAP2 is a trademark of Texas Instruments.  
Blu-ray Disc is a trademark of Blu-ray Disc Association.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011–2012, Texas Instruments Incorporated  
 
TPS54229  
SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
TRANSPORT  
TA  
PACKAGE  
ORDERABLE PART NUMBER  
PIN  
MEDIA  
TPS54229DDA  
Tube  
–40°C to 85°C  
DDA  
8
TPS54229DDAR  
Tape and Reel  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
(1)  
VALUE  
UNIT  
MIN  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–2  
MAX  
20  
VIN, EN  
V
V
VBST  
26  
VBST (10 ns transient)  
VBST (vs SW)  
VFB, SS  
28  
V
Input voltage range  
Output voltage range  
6.5  
6.5  
20  
V
V
SW  
V
SW (10 ns transient)  
VREG5  
–3  
22  
V
–0.3  
–0.3  
–0.2  
6.5  
0.3  
0.2  
2
V
GND  
V
Voltage from GND to thermal pad, Vdiff  
Human Body Model (HBM)  
Charged Device Model (CDM)  
V
kV  
V
Electrostatic discharge  
500  
150  
150  
Operating junction temperature, TJ  
Storage temperature, Tstg  
–40  
–55  
°C  
°C  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
THERMAL INFORMATION  
TPS54229  
THERMAL METRIC  
UNITS  
DDA (8 PINS)  
θJA  
Junction-to-ambient thermal resistance  
45.3  
54.8  
16.2  
6.6  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
16.0  
8.5  
θJCbot  
2
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SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
4.5  
MAX  
18  
UNIT  
VIN  
Supply input voltage range  
V
VBST  
–0.1  
-0.1  
–0.1  
–0.1  
–0.1  
–0.1  
–1.8  
–3  
24  
VBST (10 ns transient)  
27  
VBST(vs SW)  
5.7  
5.7  
18  
SS  
VI  
Input voltage range  
EN  
V
VFB  
5.5  
18  
SW  
SW (10 ns transient)  
GND  
21  
–0.1  
–0.1  
0
0.1  
5.7  
10  
VO  
IO  
Output voltage range  
VREG5  
V
Output Current range  
IVREG5  
mA  
°C  
°C  
TA  
TJ  
Operating free-air temperature  
Operating junction temperature  
–40  
–40  
85  
150  
ELECTRICAL CHARACTERISTICS  
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)  
PARAMETER  
SUPPLY CURRENT  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VIN current, TA = 25°C, EN = 5 V,  
VFB = 0.8 V  
IVIN  
Operating - non-switching supply current  
840  
5.8  
1200  
10  
μA  
μA  
IVINSDN  
Shutdown supply current  
VIN current, TA = 25°C, EN = 0 V  
LOGIC THRESHOLD  
VENH  
VENL  
REN  
EN high-level input voltage  
EN  
1.6  
220  
749  
V
V
EN low-level input voltage  
EN pin resistance to GND  
EN  
0.6  
VEN = 12 V  
440  
880  
kΩ  
VFB VOLTAGE AND DISCHARGE RESISTANCE  
VFBTH  
IVFB  
VFB threshold voltage  
VFB input current  
TA = 25°C, VO = 1.05 V, continuous mode  
VFB = 0.8 V, TA = 25°C  
765  
0
781  
mV  
±0.1  
μA  
VREG5 OUTPUT  
TA = 25°C, 6.0 V < VIN < 18 V,  
0 < IVREG5 < 5 mA  
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C(1)  
VVREG5  
VREG5 output voltage  
5.5  
60  
V
IVREG5  
Output current  
mA  
MOSFET  
RDS(on)h  
RDS(on)l  
High side switch resistance  
Low side switch resistance  
25°C, VBST - SW = 5.5 V(1)  
25°C(1)  
160  
110  
mΩ  
mΩ  
CURRENT LIMIT  
Iocl  
Current limit  
L out = 2.2 μH(1)  
2.5  
3.3  
4.7  
A
(1) Not production tested.  
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ELECTRICAL CHARACTERISTICS (continued)  
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)  
PARAMETER  
THERMAL SHUTDOWN  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
(2)  
Shutdown temperature  
165  
35  
TSDN  
Thermal shutdown threshold  
°C  
(2)  
Hysteresis  
ON-TIME TIMER CONTROL  
tON  
On time  
VIN = 12 V, VO = 1.05 V  
TA = 25°C, VFB = 0.7 V(2)  
155  
260  
ns  
ns  
tOFF(MIN)  
Minimum off time  
SOFT START  
ISSC  
SS charge current  
VSS = 1V  
4.2  
0.1  
6.0  
0.2  
7.8  
μA  
ISSD  
SS discharge current  
VSS = 0.5 V  
mA  
UVLO  
Wake up VREG5 voltage  
Hysteresis VREG5 voltage  
3.75  
0.32  
UVLO  
UVLO threshold  
V
(2) Not production tested.  
4
Copyright © 2011–2012, Texas Instruments Incorporated  
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SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
DEVICE INFORMATION  
DDA PACKAGE  
(TOP VIEW)  
1
2
3
4
8
7
6
5
VBST  
VIN  
SS  
TPS54229  
DDA  
EN  
VREG5  
VFB  
(HSOP8)  
SW  
Power PAD  
GND  
PIN FUNCTIONS  
PIN  
DESCRIPTION  
NAME  
NO.  
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW  
pins. An internal diode is connected between VREG5 and VBST.  
VBST  
1
VIN  
SW  
2
3
Input voltage supply pin.  
Switch node connection between high-side NFET and low-side NFET.  
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at  
a single point.  
GND  
4
5
6
VFB  
Converter feedback input. Connect to output voltage with feedback resistor divider.  
5.5 V power supply output. A capacitor (typical 0.47µF) should be connected to GND. VREG5 is not  
active when EN is low.  
VREG5  
EN  
SS  
7
8
Enable input control. EN is active high and must be pulled up to enable the device.  
Soft-start control. An external capacitor should be connected to GND.  
Exposed Thermal  
Pad  
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to  
GND.  
Back side  
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FUNCTIONAL BLOCK DIAGRAM  
EN  
EN  
VIN  
7
Logic  
VIN  
2
1
VREG5  
VBST  
Control Logic  
+
+
Ref  
SS  
PWM  
1 shot  
VO  
SW  
VFB  
VREG5  
SS  
3
5
-
XCON  
ON  
VREG5  
Ceramic  
Capacitor  
6
8
SGND  
SS  
4
Softstart  
GND  
PGND  
SGND  
+
SW  
PGND  
OCP  
-
VIN  
UVLO  
TSD  
Protection  
Logic  
VREG5  
UVLO  
Ref  
REF  
6
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SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
OVERVIEW  
The TPS54229 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It  
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output  
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low  
ESR output capacitors including ceramic and special polymer types.  
DETAILED DESCRIPTION  
PWM Operation  
The main control loop of the TPS54229 is an adaptive on-time pulse width modulation (PWM) controller that  
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with  
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with  
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.  
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one  
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to  
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The  
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the  
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need  
for ESR induced output ripple from D-CAP2™ mode control.  
PWM Frequency and Adaptive On-Time Control  
TPS54229 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The  
TPS54229 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to  
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the  
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.  
Soft Start and Pre-Biased Soft Start  
The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor  
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.  
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is  
6 μA.  
C
(nF) x V  
´1.1  
C
(nF) x 0.765´1.1  
SS  
REF  
SS  
t
(ms) =  
=
SS  
I
(mA)  
6
SS  
(1)  
The TPS54229 contains a unique circuit to prevent current from being pulled from the output during startup if the  
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start  
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting  
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-  
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This  
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps  
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal  
mode operation.  
Current Protection  
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The  
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This  
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature  
compensated.  
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,  
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current  
decreases linearly. The average value of the switch current is the load current IOUT. The TPS54229 constantly  
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.  
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented  
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the  
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching  
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cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in  
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL  
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the  
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the  
higher value.  
There are some important considerations for this type of over-current protection. The load current one half of the  
peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the  
output voltage tends to fall as the demanded load current may be higher than the current available from the  
converter. This may cause the output voltage to fall. When the over current condition is removed, the output  
voltage will return to the regulated value. This protection is non-latching.  
UVLO Protection  
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower  
than UVLO threshold voltage, the TPS54229 is shut off. This is protection is non-latching.  
Thermal Shutdown  
TPS54229 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),  
the device is shut off. This is non-latch protection.  
8
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SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
TYPICAL CHARACTERISTICS  
VIN = 12 V, TA = 25°C (unless otherwise noted).  
12  
1200  
1000  
800  
10  
8
V = 12 V  
I
V = 12 V  
I
6
600  
4
400  
200  
2
0
0
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
T
- Junction Temperature - °C  
T
- Junction Temperature - °C  
J
J
Figure 1. VIN CURRENT vs JUNCTION TEMPERATURE  
Figure 2. VIN SHUTDOWN CURRENT vs  
JUNCTION TEMPERATURE  
50  
1.07  
1.06  
1.05  
1.04  
1.03  
45  
40  
35  
30  
25  
20  
15  
10  
5
V = 18 V  
V = 12 V  
I
I
V = 5 V  
I
V = 18 V  
I
0
0
0.5  
1
1.5  
2
0
5
10  
15  
20  
I
- Output Current - A  
V - Input Voltage - V  
I
O
Figure 3. EN CURRENT vs EN VOLTAGE  
Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT  
1.07  
1.06  
1.05  
1.04  
1.03  
Vout = 50 mV/div  
I
= 0 A  
O
I
= 1 A  
O
Iout = 1 A/div  
0
5
10  
15  
20  
t - Time - 100 ms  
V - Input Voltage - V  
I
Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE  
Figure 6. 1.05-V, 50-mA to 2-A LOAD TRANSIENT  
RESPONSE  
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TYPICAL CHARACTERISTICS  
VIN = 12 V, TA = 25°C (unless otherwise noted).  
100  
V
= 3.3 V  
O
V
= 1.8 V  
V
= 2.5 V  
O
O
EN = 10 V/div  
90  
80  
70  
60  
VREG5 = 5 V/div  
V
= 0.5 V/div  
O
50  
40  
0
0.5  
1
- Output Current - A  
1.5  
2
t - Time - 1 ms  
I
O
Figure 7. START-UP WAVE FORM  
Figure 8. EFFICIENCY vs OUTPUT CURRENT  
900  
850  
800  
750  
700  
650  
600  
550  
500  
900  
850  
800  
750  
700  
650  
600  
550  
500  
450  
400  
V
= 5 V  
O
V
= 3.3 V  
O
V
= 3.3 V  
O
V
= 2.5 V  
O
V
= 1.05 V  
V
O
V
= 1.8 V  
V
= 1.05 V  
O
= 1.2 V  
O
O
V = 1.5 V  
O
V
= 1.8 V  
O
450  
400  
0
0.5  
1
1.5  
2
0
5
10  
V - Input Voltage - V  
15  
20  
I
- Output Current - A  
O
I
Figure 9. SWITCHING FREQUENCY vs INPUT VOLTAGE  
Figure 10. SWITCHING FREQUENCY vs  
OUTPUT CURRENT  
V
= 1.05 V  
V
= 1.05 V  
O
O
V
= 50 mV/div  
O
V
= 10 mV/div  
O
SW = 5 V/div  
SW = 5 V/div  
t - Time - 400 ns  
Figure 12. VOLTAGE RIPPLE AT INPUT (IO = 2 A)  
t - Time - 400 ns  
Figure 11. VOLTAGE RIPPLE AT OUTPUT (IO = 2 A)  
10  
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SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
TYPICAL CHARACTERISTICS  
VIN = 12 V, TA = 25°C (unless otherwise noted).  
0.78  
VIN = 12 V  
IO = 1 A  
0.775  
0.77  
0.765  
0.76  
0.755  
0.75  
−40  
−20  
0
20  
40  
60  
80  
100  
120  
Temperature (°C)  
G000  
Figure 13. VFB VOLTAGE vs JUNCTION TEMPERATURE  
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DESIGN GUIDE  
Step By Step Design Procedure  
To begin the design process, you must know a few application parameters:  
Input voltage range  
Output voltage  
Output current  
Output voltage ripple  
Input voltage ripple  
U1  
TPS54229DDA  
Figure 14. Shows the schematic diagram for this design example.  
Output Voltage Resistors Selection  
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use  
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT  
.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more  
susceptible to noise and voltage errors from the VFB input current will be more noticeable.  
æ
ö
÷
÷
R1  
ç
= 0.765 x 1 +  
V
OUT  
ç
÷
÷
ø
ç
è
R2  
(2)  
Output Filter Selection  
The output filter used with the TPS54229 is an LC circuit. This LC filter has double pole at:  
1
F
P
=
2p L  
x C  
OUT  
OUT  
(3)  
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal  
gain of the TPS54229. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls  
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that  
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the  
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole  
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the  
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the  
values recommended in Table 1  
12  
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Table 1. Recommended Component Values  
Output Voltage (V)  
R1 (kΩ)  
6.81  
8.25  
12.7  
21.5  
30.1  
49.9  
73.2  
124  
R2 (kΩ)  
22.1  
22.1  
22.1  
22.1  
22.1  
22.1  
22.1  
22.1  
22.1  
C4 (pF)  
L1 (µH)  
2.2  
C8 + C9 + C10 (µF)  
20 - 68  
1
1.05  
1.2  
1.5  
1.8  
2.5  
3.3  
5
2.2  
20 - 68  
2.2  
20 - 68  
2.2  
20 - 68  
5 - 22  
5 - 22  
5 - 22  
5 - 22  
5 - 22  
3.3  
20 - 68  
3.3  
20 - 68  
3.3  
20 - 68  
4.7  
20 - 68  
6.5  
165  
4.7  
20 - 68  
Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output  
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by  
adding a feed forward capacitor (C4) in parallel with R1  
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,  
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak  
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for  
fSW  
.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS  
current of Equation 6.  
V
- V  
V
IN(max)  
OUT  
OUT  
I
=
x
IPP  
x fSW  
V
L
IN(max)  
O
(4)  
(5)  
(6)  
I
lpp  
I
= I  
+
Ipeak  
O
2
1
2
2
I
=
I
+
I
Lo(RMS)  
O
IPP  
12  
For this design example, the calculated peak current is 2.311 A and the calculated RMS current is 2.009 A. The  
inductor used is a TDK CLF7045T-2R2M with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.  
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54229 is intended for use  
with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to  
determine the required RMS current rating for the output capacitor.  
V
x (V - V  
)
OUT  
IN  
OUT  
I
=
Co(RMS)  
12 x V x L  
IN  
x
fSW  
O
(7)  
For this design three TDK C3216X5R0J106M 10µF output capacitors are used. The typical ESR is 2 mΩ each.  
The calculated RMS current is 0.19 A and each output capacitor is rated for 4A.  
Input Capacitor Selection  
The TPS54229 requires an input decoupling capacitor and a bulk capacitor is needed depending on the  
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF  
capacitor (C3) is required to provide additional high frequency filtering and insure accurate current limit operation.  
This capacitor must be placed as close to the IC pins 2 (VIN) and 4 (GND) as possible. The capacitor voltage  
rating needs to be greater than the maximum input voltage.  
Bootstrap Capacitor Selection  
A 0.1µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is  
recommended to use a ceramic capacitor.  
Copyright © 2011–2012, Texas Instruments Incorporated  
13  
Product Folder Link(s): TPS54229  
 
 
 
 
TPS54229  
SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
www.ti.com  
VREG5 Capacitor Selection  
A 0.47µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is  
recommended to use a ceramic capacitor.  
THERMAL INFORMATION  
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external  
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be  
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the  
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a  
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated  
circuit (IC).  
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating  
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.  
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.  
The exposed thermal pad dimensions for this package are shown in the following illustration.  
Figure 15. Thermal Pad Dimensions (Top View)  
14  
Copyright © 2011–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS54229  
TPS54229  
www.ti.com  
SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
LAYOUT CONSIDERATIONS  
1. Keep the input switching current loop as small as possible.  
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and  
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the  
feedback pin of the device.  
3. Keep analog and non-switching components away from switching components.  
4. Make a single point connection from the signal ground to power ground.  
5. Do not allow switching current to flow under the device.  
6. Keep the pattern lines for VIN and PGND broad.  
7. Exposed pad of device must be connected to PGND with solder.  
8. VREG5 capacitor should be placed near the device, and connected PGND.  
9. Output capacitor should be connected to a broad pattern of the PGND.  
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.  
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog ground  
trace.  
12. Providing sufficient vias for VIN, SW and PGND connection.  
13. VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible to  
the device.  
14. Performance based on four layer printed circuit board.  
Copyright © 2011–2012, Texas Instruments Incorporated  
15  
Product Folder Link(s): TPS54229  
TPS54229  
SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
www.ti.com  
VIA to Power Ground Plane  
VIA to SW Copper Pour on Bottom  
or Internal Layer  
ANALOG  
GROUND  
TRACE  
VIN  
VIN  
VIN  
HIGH FREQENCY  
BYPASS  
BOOST  
CAPACITOR  
INPUT  
BYPASS  
CAPACITOR CAPACITOR  
VBST  
VIN  
SS  
TO ENABLE  
CONTROL  
EN  
SW  
VREG5  
VFB  
GND  
SLOW  
START  
CAP  
BIAS  
CAP  
EXPOSED  
THERMAL PAD  
AREA  
POWER  
GROUND  
FEEDBACK  
RESISTORS  
OUTPUT  
INDUCTOR  
SW node copper pour  
area on internal or  
bottom layer  
POWER  
GROUND  
Connection to  
POWER GROUND  
on internal or  
bottom layer  
OUTPUT  
FILTER  
CAPACITOR  
VOUT  
Figure 16. PCB Layout  
16  
Copyright © 2011–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS54229  
TPS54229  
www.ti.com  
SLVSAZ8A SEPTEMBER 2011REVISED MARCH 2012  
REVISION HISTORY  
Changes from Original (September 2011) to Revision A  
Page  
Removed (SWIFT™) from the data sheet title ..................................................................................................................... 1  
Deleted from ELECTRICAL CHARACTERISTICS table, VLN5 and VLD5, deleted VVREG5 MIN and MAX values .................. 3  
Added in ELECTRICAL CHARACTERISTICS table, IVREG5 and RDS(on)h and RDS(on)l footnote references ........................... 3  
Added in ELECTRICAL CHARACTERISTICS table, tOFF(MIN) footnote reference and delete MAX value ............................ 4  
Deleted from ELECTRICAL CHARACTERISTICS, UVLO MIN and MAX values ................................................................ 4  
Added TYPICAL CHARACTERISTICS Condition ................................................................................................................ 9  
Copyright © 2011–2012, Texas Instruments Incorporated  
17  
Product Folder Link(s): TPS54229  
PACKAGE OPTION ADDENDUM  
www.ti.com  
21-Nov-2011  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TPS54229DDA  
ACTIVE SO PowerPAD  
ACTIVE SO PowerPAD  
DDA  
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAUAGLevel-2-260C-1 YEAR  
TPS54229DDAR  
DDA  
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAUAGLevel-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-May-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS54229DDAR  
SO  
Power  
PAD  
DDA  
8
2500  
330.0  
12.8  
6.4  
5.2  
2.1  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-May-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SO PowerPAD DDA  
SPQ  
Length (mm) Width (mm) Height (mm)  
366.0 364.0 50.0  
TPS54229DDAR  
8
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard  
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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Copyright © 2012, Texas Instruments Incorporated  
配单直通车
TPS54229DDAR产品参数
型号:TPS54229DDAR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:SOIC
包装说明:HLSOP, SOP8,.25
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:8 weeks
风险等级:1.69
Is Samacsys:N
其他特性:OPERATES IN ADJUSTABLE MODE FROM 0.76 TO 7V
模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION
最大输入电压:18 V
最小输入电压:4.5 V
标称输入电压:12 V
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.9 mm
湿度敏感等级:2
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
最大输出电流:4.7 A
最大输出电压:7 V
最小输出电压:0.76 V
标称输出电压:5.5 V
封装主体材料:PLASTIC/EPOXY
封装代码:HLSOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度(摄氏度):260
认证状态:Not Qualified
座面最大高度:1.7 mm
子类别:Switching Regulator or Controllers
标称供电电压 (Vsup):12 V
表面贴装:YES
切换器配置:BUCK
最大切换频率:650 kHz
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm
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