TPS61189RTJR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

TPS61193

ZHCSEP0C – OCTOBER 2015 – REVISED FEBRUARY 2021

TPS61193 高性能三通道 LED 驱动器

1 特性

2 应用

•

输入电压工作范围：4.5V 至 40V

三路高精度电流阱

•

控制面板中的工业背光系统

工业 PC

测试和测量设备

– 电流匹配度为 1%（典型值）

– LED 灯串电流高达 100mA/通道

– 输出可在外部合并，从而提高电流能力

在 100Hz 时具有 10 000:1 的高调光比

用于 LED 灯串电源的集成升压/SEPIC 转换器

3 说明

TPS61193 是一款高效、低 EMI、易于使用的 LED 驱

动器，可灵活支持各类应用。该器件具有三路高精度电

流阱，可组合在一起使用，以提高电流能力。

•

– 输出电压高达 45V

– 开关频率为 300kHz 至 2.2MHz

– 开关同步输入

– 扩频，以实现更低的 EMI

丰富的故障检测功能

TPS61193 配备的集成式 DC-DC 转换器支持升压和

SEPIC 工作模式。转换器可基于 LED 电流阱余量电压

提供自适应输出电压控制。该特性可在所有条件下将电

压调节到能够满足需要的最低水平，从而更大限度降低

功耗。对于 EMI 控制，DC-DC 转换器支持针对开关频

率进行扩频以及使用专用引脚实现外部同步。

•

– 故障输出

– 输入电压 OVP、UVLO 和 OCP

– 开路和短路 LED 故障检测

– 热关断保护

TPS61193 具有 4.5V 至 40V 的宽输入电压范围，可为

各种不同应用提供可靠支持。TPS61193 集成了丰富的

故障检测功能。对于 100Hz 输入 PWM 频率，该器件

支持高达 10 000:1 的 PWM 亮度调光比率。

•

有效减少外部组件数

空白

L1

D1

V_OUTup to 45 V

V_IN4.5...40 V

器件信息⁽¹⁾

C

IN

封装尺寸（标称值）

器件型号

TPS61193

封装

C

OUT

HTSSOP (20)

6.50mm × 4.40mm

R2

R1

SW

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

FB

C

FB

VIN

100

95

90

85

80

75

70

Up to 100 mA/string

LDO

C_LDO

OUT1

TPS61193

OUT2

OUT3

R_FSET

FSET

SYNC

BRIGHTNESS

EN

65

PWM

VIN=5V

VIN=8V

VIN=12V

VIN=16V

60

VDDIO/EN

FAULT

55

50

ISET

0

10

20

30

40

50

60

Brightness (%)

70

80

90 100

PGND

GND PAD

D001

R_ISET

系统效率

简化版原理图

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAF4

TPS61193

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ZHCSEP0C – OCTOBER 2015 – REVISED FEBRUARY 2021

Table of Contents

7.2 Functional Block Diagram......................................... 11

7.3 Feature Description...................................................12

7.4 Device Functional Modes..........................................18

8 Application and Implementation..................................20

8.1 Application Information............................................. 20

8.2 Typical Applications.................................................. 20

9 Power Supply Recommendations................................25

10 Layout...........................................................................26

10.1 Layout Guidelines................................................... 26

10.2 Layout Example...................................................... 27

11 Device and Documentation Support..........................28

11.1 Device Support........................................................28

11.2 Documentation Support.......................................... 28

11.3 接收文档更新通知................................................... 28

11.4 支持资源..................................................................28

11.5 Trademarks............................................................. 28

11.6 静电放电警告...........................................................28

11.7 术语表..................................................................... 28

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics^{(1) (2)}....................................5

6.6 Internal LDO Electrical Characteristics....................... 5

6.7 Protection Electrical Characteristics........................... 6

6.8 Current Sinks Electrical Characteristics......................6

6.9 PWM Brightness Control Electrical Characteristics.... 6

6.10 Boost and SEPIC Converter Characteristics............ 7

6.11 Logic Interface Characteristics..................................7

6.12 Typical Characteristics..............................................8

7 Detailed Description......................................................10

7.1 Overview...................................................................10

Information.................................................................... 28

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (June 2017) to Revision C (February 2021)

更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1

• Updated Device states section......................................................................................................................... 18

Page

•

Changes from Revision A (September 2016) to Revision B (June 2017)

Page

• Enhanced pin descriptions for pins 3, 10, and 16 in Pin Functions table........................................................... 3

• Deleted "I_OUT= 100 mA" from t_ON/OFFrow of PWM Brightness Control Electrical Characteristics ....................6

• Changed "0.5" from MAX to TYP column in t_ON/OFFrow of PWM Brightness Control Electrical

Characteristics ; add note 1 to PWM Brightness Control Electrical Characteristics .......................................... 6

• Added table note 1 for Boost and SEPIC Converter Characteristics .................................................................7

• Deleted "Initial DC-DC voltage is about 88% of V_{MAX BOOST}." from Integrated DC-DC Converter; change

wording in last sentence before 方程式 1 ........................................................................................................ 12

• Changed 方程式 1 and added "K" eq definitions; added new paragraph after 图 7-1 ..................................... 12

• Added new paragraph before 节 7.3.2 .............................................................................................................12

• Deleted "Dimming ratio is calculated as ratio between the input PWM period and minimum on/off time (0.5

µs). " from Brightness Control ..........................................................................................................................14

Changes from Revision * (October 2015) to Revision A (September 2016)

Page

•

更改了特性中若干项的一些措辞........................................................................................................................ 1

将“在 200Hz 时具有 10 000:1 的高调光比”更改为“在 100Hz 时具有 10 000:1 的高调光比”..................... 1

添加了说明部分中第一段的最后一句................................................................................................................. 1

将“200Hz 时的调光比率为 10 000:1”更改为“100Hz 时的调光比率为 10 000:1”........................................1

添加了说明部分的最后一句................................................................................................................................1

• Added standard footnotes for the ESD Ratings table ........................................................................................4

• Added Figures 7 and 8 - new graphs..................................................................................................................8

2

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5 Pin Configuration and Functions

VIN

1

2

3

4

5

6

7

8

9

20

19

VIN

NC

LDO

FSET

18 SW

PGND

VDDIO/EN

FAULT

17

16 FB

SYNC

PWM

15

14

13

12

11

OUT1

OUT2

OUT3

GND

NC

GND

EP*

ISET 10

GND

*EXPOSED PAD

图 5-1. PWP Package 20-Pin TSSOP With Exposed Thermal Pad Top View

表 5-1. Pin Functions

NAME

TYPE⁽¹⁾

DESCRIPTION

NO.

1

VIN

A

Input power pin

2

LDO

Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free GND.

DC-DC (boost or SEPIC) switching frequency setting resistor; for normal operation, resistor value from

24 kΩ to 219 kΩ must be connected between this pin and ground.

3

FSET

A

4

5

VDDIO/EN

FAULT

I

Enable input for the device as well as supply input (VDDIO) for digital pins

Fault signal output. If unused, the pin may be left floating.

OD

Input for synchronizing boost. If synchronization is not used, connect this pin to GND to disable spread

spectrum or to VDDIO/EN to enable spread spectrum.

6

SYNC

I

7

8

9

PWM

NC

PWM dimming input.

No connect

—

GND

G

Ground.

LED current setting resistor; for normal operation, resistor value from 24 kΩ to 129 kΩ must be

connected between this pin and ground.

10

ISET

A

11

12

13

GND

G

A

Ground

OUT3

Current sink output; this pin must be connected to GND if not used.

Current sink output

This pin must be connected to GND if not used.

14

15

16

OUT2

OUT1

FB

A

Current sink output

This pin must be connected to GND if not used.

Boost/SEPIC feedback input; for normal operation this pin must be connected to the middle of a resistor

divider between VOUT and ground using feedback resistor values between 5 kΩ and 150 kΩ.

17

18

19

20

PGND

SW

G

A

DC-DC (boost or SEPIC) power ground

DC-DC (boost or SEPIC) switch pin

No connect

NC

VIN

Input power pin

(1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

MAX

UNIT

VIN, SW, FB

50

45

Voltage on pins

OUT1, OUT2, OUT3

V

LDO, SYNC, FSET, ISET, PWM, VDDIO/EN, FAULT

5.5

Continuous power dissipation⁽³⁾

Internally Limited

(4)

Ambient temperature range T_A

Junction temperature range T_J

125

°C

–40

(4)

150

Maximum lead temperature (soldering)

Storage temperature, T_stg

See⁽⁵⁾

150

°C

–65

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pins.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 165°C (typical)

and disengages at T_J= 145°C (typical).

(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature

may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature

(T_J-MAX-OP= 150°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal

resistance of the part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

(5) For detailed soldering specifications and information, refer to PowerPAD™ Thermally Enhanced Package.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per JESD22-A114, JS-001⁽¹⁾

All other pins

Corner pins (1,10,11,20)

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JESD22-C101

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VIN

4.5

0

45

SW

Voltage on pins

OUT1, OUT2, OUT3

0

40

V

FB, FSET, LDO, ISET, VDDIO/EN, FAULT

SYNC, PWM

0

5.25

0

VDDIO/EN

(1) All voltages are with respect to the potential at the GND pins.

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6.4 Thermal Information

TPS61193

THERMAL METRIC⁽¹⁾

PWP (TSSOP)

20 PINS

44.2

UNIT

R_θJA

R_θJCtop

R_θJB

ψ_JT

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance

°C/W

26.5

Junction-to-board thermal resistance

22.4

0.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

22.2

ψ_JB

R_θJCbot

2.5

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

6.5 Electrical Characteristics^{(1) (2)}

T_J= −40°C to +125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Device disabled, V_VDDIO/EN= 0 V, V_IN

= 12 V

Standby supply current

4.5

20

μA

I_Q

V_IN= 12 V, V_OUT= 26 V, output

current 80 mA/channel, converter

ƒ_SW= 300 kHz

Active supply current

5

12

mA

V_{POR_R}

V_{POR_F}

T_TSD

Power-on reset rising threshold

LDO pin voltage

2.7

V

Power-on reset falling threshold LDO pin voltage

Thermal shutdown threshold

1.5

150

165

20

175

°C

T_{TSD_HYST}

Thermal shutdown hysteresis

(1) All voltages are with respect to the potential at the GND pins.

(2) Minimum and maximum limits are specified by design, test, or statistical analysis.

6.6 Internal LDO Electrical Characteristics

T_J= −40°C to +125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

4.15

120

TYP

4.3

300

50

MAX

4.55

430

UNIT

V

V_LDO

V_DR

Output voltage

V_IN= 12 V

Dropout voltage

mV

mA

I_SHORT

Short circuit current

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6.7 Protection Electrical Characteristics

T_J= −40°C to +125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

42

4

MAX

UNIT

V

V_OVP

VIN OVP threshold voltage

VIN UVLO

41

44

V_UVLO

V

V_{UVLO_HYST}

VIN UVLO hysteresis

LED short detection threshold

100

6

mV

V

5.6

7

6.8 Current Sinks Electrical Characteristics

T_J= −40°C to +125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

0.1

MAX UNIT

I_LEAKAGE

I_MAX

Leakage current

Outputs OUT1 to OUT3 , V_OUTx= 45 V

OUT1, OUT2, OUT3

5

µA

Maximum current

100

mA

I_OUT

Output current accuracy

Output current matching⁽¹⁾

Saturation voltage⁽²⁾

I_OUT= 100 mA

5%

0.7

−5%

I_MATCH

V_SAT

I_OUT= 100 mA, PWM duty =100%

I_OUT= 100 mA

1%

0.4

V

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current sinks on the part (OUTx), the following are determined:

the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching

number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts.

LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

6.9 PWM Brightness Control Electrical Characteristics

T_J= −40°C to +125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Hz

PWM input frequency

Minimum on/off time⁽¹⁾

100

20 000

ƒ_PWM

t_ON/OFF

0.5

µs

(1) This specification is not ensured by ATE.

6

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6.10 Boost and SEPIC Converter Characteristics

T_J= −40°C to +125°C (unless otherwise noted). Unless otherwise specified: V_IN= 12 V, V_EN/VDDIO= 3.3 V, L = 22 μH, C_IN

=

2 × 10-μF ceramic and 33-μF electrolytic, C_OUT= 2 × 10-μF ceramic and 33-μF electrolytic, D = NRVB460MFS, ƒ_SW

=

300 kHz.

PARAMETER

Input voltage

TEST CONDITIONS

MIN

4.5

6

TYP

MAX

40

UNIT

V_IN

V

V_OUT

Output voltage

45

Minimum switching frequency

(central frequency if spread

spectrum is enabled)

300

kHz

ƒ_{SW_MIN}

Defined by R_FSETresistor

Maximum switching frequency

(central frequency if spread

spectrum is enabled)

2 200

ƒ_{SW_MAX}

V_OUT/V_IN

T_OFF

Conversion ratio

10

55

Minimum switch OFF time⁽¹⁾

SW current limit

ns

A

ƒ_SW≥ 1.15 MHz

I_{SW_MAX}

R_DSON

1.8

2

2.2

FET R_DSON

Pin-to-pin

240

400

mΩ

kHz

ns

f_SYNC

External SYNC frequency

External SYNC minimum on time⁽¹⁾

External SYNC minimum off time⁽¹⁾

300

2 200

t_{SYNC_ON_MIN}

t_{SYNC_OFF_MIN}

150

ns

(1) This specification is not ensured by ATE.

6.11 Logic Interface Characteristics

T_J= −40°C to +125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC INPUT VDDIO/EN

V_IL

V_IH

I_I

Input low level

Input high level

Input current

0.4

V

1.65

5

30

0.2 × VDDIO/EN

1

µA

−1

LOGIC INPUT SYNC/FSET, PWM

V_IL

V_IH

I_I

Input low level

Input high level

Input current

V

0.8 × VDDIO/EN

−1

μA

LOGIC OUTPUT FAULT

V_OL

Output low level

Output leakage current

Pullup current 3 mA

V = 5.5 V

0.3

0.5

1

V

I_LEAKAGE

μA

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6.12 Typical Characteristics

Unless otherwise specified: D = NRVB460MFS, T = 25°C

1000

900

800

700

600

500

1000

900

800

700

600

500

400

300

200

Vboost = 22 V

Vboost = 30 V

Vboost = 37 V

25

Vboost = 22 V

400

300

200

Vboost = 30V

Vboost = 37 V

5

10

15

20

30

5

10

15

20

25

30

Input Voltage (V)

C001

C002

DC Load (PWM = 100%)

ƒ_SW= 300 kHz

L = 33 μH

ƒ_SW= 800 kHz

L = 15 μH

C_INand C_OUT= 33 µF + 2 × 10 µF (ceramic)

C_INand C_OUT= 2 × 10 µF (ceramic)

图 6-1. Maximum Boost Current

图 6-2. Maximum Boost Current

1000

900

800

700

600

500

400

300

200

1000

900

800

700

600

500

400

300

200

Vboost = 22 V

Vboost = 30 V

Vboost = 37 V

Vboost = 22 V

Vboost = 30 V

Vboost = 37 V

5

10

15

20

25

30

5

10

15

20

25

30

Input Voltage (V)

C003

C004

DC Load (PWM = 100%)

ƒ_SW= 1.5 MHz

L = 8.2 μH

ƒ_SW= 2.2 MHz

C_INand C_OUT= 2 × 10 µF (ceramic)

图 6-4. Maximum Boost Current

L = 4.7 μH

C_INand C_OUT= 2 × 10 µF (ceramic)

图 6-3. Maximum Boost Current

100

80

60

40

20

0

2200

1800

1400

1000

600

200

20

60

100

140

180

220

20

40

60

80

100

120

140

160

R_FSET(kꢀ)

C009

R_ISET(kꢀ)

C005

图 6-6. Boost Switching Frequency ƒ_SWvs R_FSET

图 6-5. LED Current vs R_ISET

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6.12 Typical Characteristics (continued)

Unless otherwise specified: D = NRVB460MFS, T = 25°C

6

120

100

80

60

40

20

0

5

4

3

2

1

0

40

50

60

70

80

90

100

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Output current (mA)

Voltage (V)

C013

C014

图 6-7. LED Current Sink Matching

R_ISET= 24 kΩ

图 6-8. LED Current Sink Saturation Voltage

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7 Detailed Description

7.1 Overview

The TPS61193 is a highly integrated LED driver for medium-sized LCD backlight applications. It includes a DC-

DC with an integrated FET, supporting both boost and SEPIC modes, an internal LDO enabling direct connection

to battery without need for a pre-regulated supply and three LED current sinks. The VDDIO/EN pin provides the

supply voltage for digital IOs (PWM and SYNC inputs) and at the same time enables the device.

The switching frequency on the DC-DC converter is set by a resistor connected to the FSET pin. The maximum

voltage of the DC-DC is set by a resistive divider connected to the FB pin. For the best efficiency the output

voltage is adapted automatically to the minimum necessary level needed to drive the LED strings. This is done

by monitoring LED output voltage drop in real time. For EMI reduction and control two optional features are

available:

• Spread spectrum, which reduces EMI noise around the switching frequency and its harmonic frequencies

• DC-DC can be synchronized to an external frequency connected to SYNC pin

The three constant current sinks OUT1, OUT2, and OUT3 provide LED current up to 100 mA. Value for the

current per OUT pin is set with a resistor connected to ISET pin. Current sinks that are not used must be

connected to ground. Grounded current sink is disabled and excluded from adaptive voltage detection loop.

Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED

output PWM follows the input PWM so the output frequency is equal to the input frequency.

TPS61193 has extensive fault detection features:

• Open-string and shorted LED detections

– LED fault detection prevents system overheating in case of open or short in some of the LED strings

• V_INinput overvoltage protection

– Threshold sensing from VIN pin

• V_INinput undervoltage protection

– Threshold sensing from VIN pin

• Thermal shutdown in case of die overtemperature

Fault condition is indicated through the FAULT output pin.

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7.2 Functional Block Diagram

L

D

V_OUT

V_IN

C_IN

C_OUT

VIN

LDO

C_LDO

SW

SYNC

PGND

FB

BOOST

CONTROLLER

R_FSET

FSET

ISET

R1

R_ISET

R2

LED

CURRENT

SINKS

CURRENT

SETTING

OUT1

OUT2

PWM

VDDIO/EN

FAULT

OUT3

GND

DIGITAL BLOCKS

(FSM, ADAPTIVE VOLTAGE

CONTROL, SAFETY LOGIC

etc.)

ANALOG BLOCKS

(CLOCK GENERATOR,

VREF, TSD etc.)

VDDIO

EXPOSED PAD

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7.3 Feature Description

7.3.1 Integrated DC-DC Converter

The TPS61193 DC-DC converter generates supply voltage for the LEDs and can operate in boost mode or in

SEPIC mode. The maximum output voltage V_{OUT_MAX}is defined by an external resistive divider (R1, R2).

V_{OUT_MAX}voltage should be chosen based on the maximum voltage required for LED strings. Recommended

maximum voltage is about 30% higher than maximum LED string voltage. DC-DC output voltage is adjusted

automatically based on LED current sink headroom voltage. Maximum, minimum, and initial boost voltages can

be calculated with 方程式 1:

V

≈

’

BG

V_BOOST

=

+K ì 0.0387 ì R1+ V_BG

∆

«

÷

R2

◊

(1)

where

• V_BG= 1.2 V

• R2 recommended value is 130 kΩ

• Resistor values are in kΩ

• K = 1 for maximum adaptive boost voltage (typical)

• K = 0 for minimum adaptive boost voltage (typical)

• K = 0.88 for initial boost voltage (typical)

45

40

35

30

25

20

15

10

200

300

400

500

600

700

800

900

1000

R1 (kꢀ)

C008

图 7-1. Maximum Converter Output Voltage vs R1 Resistance

Alternatively, a T-divider can be used if resistance less than 100 kΩ is required for the external resistive divider.

Refer to Using the TPS61193EVM and TPS61193-Q1EVM Evaluation Module for details.

The converter is a current mode DC-DC converter, where the inductor current is measured and controlled with

the feedback. Switching frequency is adjustable between 250 kHz and 2.2 MHz with R_FSETresistor as 方程式 2:

ƒ_SW= 67600 / (R_FSET+ 6.4)

(2)

where

ƒ_SWis switching frequency, kHz

• R_FSETis frequency setting resistor, kΩ

•

In most cases lower frequency has higher system efficiency. DC-DC internal parameters are chosen

automatically according to the selected switching frequency (see 表 7-2) to ensure stability. In boost mode a 15-

pF capacitor C_FBmust be placed across resistor R1 when operating in 300-kHz to 500-kHz range (see Typical

Application for 3 LED Strings). When operating in the 1.8-MHz to 2.2-MHz range C_FB= 4.7 pF.

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D

V_IN

V_OUT

C_IN

C_OUT

R1

SW

OCP

ADAPTIVE

VOLTAGE

CONTROL

R2

LIGHT

LOAD

CURRENT

SENSE

OVP

RC

R

S

R

filter

FB

-

G_M

PGND

R

+

SYNC

FSET

G_M

ꢀ

F_SET

BLANK

TIME

CTRL

BOOST

OFF/BLANK

TIME

CURRENT

RAMP

OSCILLATOR

PULSE

GENERATOR

R_FSET

GENERATOR

图 7-2. Boost Block Diagram

DC-DC can be driven by an external SYNC signal between 300 kHz and 2.2 MHz. If the external synchronization

input disappears, DC-DC continues operation at the frequency defined by R_FSETresistor. When external

frequency disappears and SYNC pin level is low, converter continues operation without spread spectrum

immediately. If SYNC remains high, converter continues switching with spread spectrum enabled after 256 µs.

External SYNC frequency must be 1.2 to 1.5 times higher than the frequency defined by R_FSETresistor.

Minimum frequency setting with R_FSETis 250 kHz to support 300-kHz switching with external clock.

The optional spread spectrum feature (±3% from central frequency, 1-kHz modulation frequency) reduces EMI

noise at the switching frequency and its harmonic frequencies. When external synchronization is used, spread

spectrum is not available.

表 7-1. DC-DC Synchronization Mode

SYNC PIN INPUT

MODE

Low

High

Spread spectrum disabled

Spread spectrum enabled

300 to 2200-kHz frequency

Spread spectrum disabled, external synchronization mode

表 7-2. DC-DC Parameters⁽¹⁾

TYPICAL BOOST INPUT

AND OUTPUT

CAPACITORS (µF)

TYPICAL

INDUCTANCE (µH)

MINIMUM SWITCH

OFF TIME (ns)⁽²⁾

BLANK

TIME (ns)

CURRENT

RAMP (A/s)

CURRENT RAMP

DELAY (ns)

RANGE

FREQUENCY (kHz)

1

2

3

4

300 to 480

480 to 1150

1150 to 1650

1650 to 2200

33

15

10

4.7

2 ×10 (cer.) + 33 (electr.)

10 (cer.) + 33 (electr.)

3 × 10 (cer.)

150

60

95

70

24

43

550

300

0

40

79

3 × 10 (cer.)

40

145

0

(1) Parameters are for reference only.

(2) Due to current sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.

The converter SW pin DC current is limited to 2 A (typical). To support short-term transient conditions the current

limit is automatically increased to 2.5 A for a short period of 1.5 seconds when a 2-A limit is reached.

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Note

Application condition where the 2-A limit is exceeded continuously is not allowed. In this case the

current limit would be 2 A for 1.5 seconds followed by 2.5-A limit for 1.5 seconds, and this 3-second

period repeats.

To keep switching voltage within safe levels there is a 48-V limit comparator in the event that FB loop is broken.

7.3.2 Internal LDO

The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage for internal use. Connect a

minimum of 1-µF ceramic capacitor from LDO pin to ground, as close to the LDO pin as possible.

7.3.3 LED Current Sinks

7.3.3.1 Output Configuration

TPS61193 detects LED output configuration during start-up. Any current sink output connected to ground is

disabled and excluded from the adaptive voltage control of the DC-DC and fault detections.

7.3.3.2 Current Setting

Maximum current for the LED outputs is controlled with external R_ISETresistor. R_ISETvalue for target maximum

current can be calculated using 方程式 3:

R_ISET= 2342 / (I_OUTœ 2.5)

(3)

where

• R_ISETis current setting resistor, kΩ

• I_LEDis output current per output, mA

7.3.3.3 Brightness Control

TPS61193 controls the brightness of the display with conventional PWM. Output PWM directly follows the input

PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.

7.3.4 Protection and Fault Detections

The TPS61193 has fault detection for LED open and short, VIN input overvoltage protection (VIN_OVP) , VIN

undervoltage lockout (VIN_UVLO), and thermal shutdown (TSD).

7.3.4.1 Adaptive DC-DC Voltage Control and Functionality of LED Fault Comparators

Adaptive voltage control function adjusts the DC-DC output voltage to the minimum sufficient voltage for proper

LED current sink operation. The current sink with highest V_FLED string is detected and DC-DC output voltage

adjusted accordingly. DC-DC adaptive control voltage step size is defined by maximum voltage setting, V_STEP

=

(V_{OUT_MAX}– V_{OUT_MIN)}/ 256. Periodic down pressure is applied to the target voltage to achieve better system

efficiency.

Every LED current sink has 3 comparators for the adaptive DC-DC control and LED fault detections. Comparator

outputs are filtered, filtering time is 1 µs.

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OUT#

SHORT STRING

DETECTION LEVEL

HIGH_COMP

VOLTAGE THRESHOLD

LOWEST VOLTAGE

MID_COMP

LOW_COMP

CURRENT/PWM

CONTROL

图 7-3. Comparators for Adaptive Voltage Control and LED Fault Detection

图 7-4 shows different cases which cause DC-DC voltage increase, decrease, or generate faults. In normal

operation voltage at all the OUT# pins is between LOW_COMP and MID_COMP levels, and boost voltage stays

constant. LOW_COMP level is the minimum for proper LED current sink operation, 1.1 × V_SAT+ 0.2 V (typical).

MID_COMP level is 1.1 × V_SAT+ 1.2 V (typical) so typical headroom window is 1 V.

When voltage at all the OUT# pins increases above MID_COMP level, DC-DC voltage adapts downwards.

When voltage at any of the OUT# pins falls below LOW_COMP threshold, DC-DC voltage adapts upwards. In

the condition where DC-DC voltage reaches the maximum and there are one or more outputs still below

LOW_COMP level, an open LED fault is detected.

HIGH_COMP level, 6-V typical, is the threshold for shorted LED detection. When the voltage of one or more of

the OUT# pins increases above HIGH_COMP level and at least one of the other outputs is within the normal

headroom window, shorted LED fault is detected.

Shorted LED fault (at

least one output should

be between

LOW_COMP and

MID_COMP)

DCDC

decreases

voltage

DCDC

increases

voltage

No actions

Open LED fault when

V_OUT=V _{OUT_MAX}

Minimum

headroom

level

Shorted

LED fault

All outputs are

above headroom

window

Open LED

fault

reached

HIGH_COMP

MID_COMP

HEADROOM

WINDOW

LOW_COMP

图 7-4. Protection and DC-DC Voltage Adaptation Algorithms

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7.3.4.2 Overview of the Fault/Protection Schemes

A summary of the TPS61193 fault detection behavior is shown in 表 7-3. Detected faults (excluding LED open or

short) cause device to enter FAULT_RECOVERY state. In FAULT_RECOVERY the DC-DC and LED current

sinks of the device are disabled, and the FAULT pin is pulled low. The device recovers automatically and enters

normal operating mode (ACTIVE) after a recovery time of 100 ms if the fault condition has disappeared. When

recovery is succesful, FAULT pin is released.

If a LED fault is detected, the device continues normal operation and only the faulty string is disabled. The fault

is indicated via the FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2 µs to

20 µs. LEDs are turned off for this period but the device stays in ACTIVE mode. If VDDIO/EN is low longer, the

device goes to STANDBY and restarts when EN goes high again.

表 7-3. Fault Detections

FAULT_

RECOVERY

STATE

FAULT/

PROTECTION

FAULT

FAULT NAME

THRESHOLD

ACTION

1. Overvoltage is monitored from the beginning of soft

start. Fault is detected if the duration of overvoltage

condition is 100-µs minimum.

1. V_IN> 42 V

2. V_OUT

>

V_{SET_DCDC}+ 6..10

V.

V_{SET_DCDC}is

voltage value

defined by logic

during adaptation

2. Overvoltage is monitored from the beginning of

normal operation (ACTIVE mode). Fault is detected if

over-voltage condition duration is 560-ms minimum

(t_filter). After the first fault, detection filter time is reduced

to 50 ms for following recovery cycles. When the device

recovers and has been in ACTIVE mode for 160 ms,

filter time is increased back to 560 ms.

VIN overvoltage

protection

VIN_OVP

Yes

No

VIN

undervoltage

lockout

Detects undervoltage condition at VIN pin. Sensed in all

operating modes. Fault is detected if undervoltage

condition duration is 100-µs minimum.

Falling 3.9 V

Rising 4 V

VIN_UVLO

OPEN_LED

Detected if the voltage of one or more current sinks is

below threshold level, and DC-DC adaptive control has

reached maximum voltage. Open string is removed

from the DC-DC voltage control loop and current sink is

disabled.

Fault pin is released by toggling VDDIO/EN pin. If

VDDIO/EN is low for a period of 2 µs to 20 µs, LEDs

are turned off for this period but device stays ACTIVE. If

VDDIO/EN is low longer, device goes to STANDBY and

restarts when EN goes high again.

LOW_COMP

threshold

Open LED fault

Detected if the voltage of one or more current sinks is

above shorted string detection level and at least one

OUTx voltage is within headroom window. Shorted

string is removed from the DC-DC voltage control loop

and current sink is disabled.

Fault pin is released by toggling VDDIO/EN pin. If

VDDIO/EN is low for a period of 2…20 µs, LEDs are

turned off for this period but device stays ACTIVE. If

VDDIO/EN is low longer, device goes to STANDBY and

restarts when EN goes high again.

Shorted LED

fault

Shorted string

detection level 6 V

SHORT_LED

Yes

No

165°C

Thermal shutdown

hysteresis 20°C

Thermal shutdown is monitored from the beginning of

soft start. Die temperature must decrease by 20°C for

device to recover.

Thermal

protection

TSD

Yes

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Time is not enough to

discharge C_OUT

VIN OVERVOLTAGE

VIN OK

V_IN

V_OUT

V_{SET_DCDC}+ 6...10 V

I_OUT

FAULT

t_FILTER= 560 ms

t_RECOVERY

100 ms

=

t_SOFTSTART

t_{BOOST START}

+

t_FILTER

50 ms

=

t_RECOVERY

100 ms

=

t_SOFTSTART

+

t_FILTER

t_{BOOST START}40 - 50 ms

=

t_RECOVERY

100 ms

=

t_SOFTSTART+ t_FILTER=

t_{BOOST START}50 ms

图 7-5. V_INOvervoltage Protection (DC-DC OVP)

VIN OVP threshold

V_IN

DCDC OVP threshold

FB

tt_SOFTSTART+t

FAULT

tt_RECOVERY= 100 mst

tt_{BOOST STARTUP}

t

图 7-6. V_INOvervoltage Protection (V_INOVP)

UVLO rising threshold

UVLO falling threshold

V_IN

FB

tt_SOFTSTART+t

tt_{BOOST STARTUP}

FAULT

tt_RECOVERY= 100 mst

t

图 7-7. V_INUndervoltage Lockout

V_{OUT_MAX}

V_OUT

OUT# pin

Other LEDs

OUT# pin

Open LED

LOW_COMP level

t = 2...20 µs

VDDIO/EN

FAULT

图 7-8. LED Open Fault

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MID_COMP level

LOW_COMP level

OUT# pin

Other LEDs

OUTT# pin

Shorted LED

HIGH_COMP level

t = 2...20 µs

VDDIO/EN

FAULT

图 7-9. LED Short Fault

7.4 Device Functional Modes

7.4.1 Device States

The TPS61193 enters STANDBY mode when the internal LDO output rises above the power-on reset level, V_LDO

> V_POR. In STANDBY mode the device is able to detect VDDIO/EN signal. When VDDIO/EN is pulled high, the

device powers up. After start LED outputs are sensed to detect grounded outputs. Grounded outputs are

disabled and excluded from the adaptive voltage control loop of the DC-DC. Please note that the input transient

current would be maximum 1.2 mA while VDDIO/EN is powering up.

If a fault condition is detected, the device enters FAULT_RECOVERY state. Faults that cause the device to enter

FAULT_RECOVERY are listed in 表 7-3. When LED open or short is detected, the faulty string is disabled, but

device stays in ACTIVE mode.

POR=1

STANDBY

VDDIO/EN=1

VIN_OVP

100 ms

VIN_UVLO

SOFT START

65 ms

50 ms

TSD

FAULT RECOVERY

BOOST START

FAULTS

VDDIO/EN=0

NO

FAULT

RECOVERY?

FAULTS

FAULTS:

- VIN_OVP

- VIN_UVLO

- TSD

LED OUTPUT

CONFIGURATION

DETECTION

YES

ACTIVE

VDDIO/EN=0

SHUTDOWN

DC-DC AND LED CURRENT

SINKS ARE DISABLED IN

FAULT RECOVERY STATE

图 7-10. State Diagram

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T=50ꢀs

t>500ꢀs

VIN

LDO

VDDIO/EN

SYNC

Headroom adaptation

V_OUT=V_INlevel œ diode drop

V_OUT

PWM OUT

I_Q

Active mode

SOFT

START

BOOST

START

图 7-11. Timing Diagram for the Typical Start-Up and Shutdown

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS61193 supports input voltage range from 4.5 V to 40 V. Device internal circuitry is powered from the

integrated LDO.

The TPS61193 uses a simple four-wire control:

• VDDIO/EN for enable

• PWM input for brightness control

• SYNC pin for boost synchronisation (optional)

• FAULT output to indicate fault condition (optional)

8.2 Typical Applications

8.2.1 Typical Application for 3 LED Strings

图 8-1 shows the typical application for TPS61193 which supports 3 LED strings with maximum current 100 mA,

with a boost switching frequency of 300 kHz.

VIN

4.5...28 V

L1

D1

Up to 37 V

C_{IN BOOST}

C

OUT

R2

R1

SW

FB

C

FB

VIN

C

IN

Up to 100 mA/string

LDO

C_LDO

R_FSET

OUT1

OUT2

OUT3

TPS61193

FSET

SYNC

PWM

BRIGHTNESS

EN

VDDIO/EN

FAULT

ISET

R3

PGND GND PAD

R_ISET

VDDIO

图 8-1. Three Strings 100-mA/String Configuration

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8.2.1.1 Design Requirements

DESIGN PARAMETER

VALUE

4.5 V – 28 V

3P8S LEDs (30 V)

100 mA

V_INvoltage range

LED string

LED string current

Maximum boost voltage

37 V

Boost switching frequency

300 kHz

External boost sync

not used

Boost spread spectrum

enabled

L1

C_IN

33 μH

100 µF, 50 V

C_{IN BOOST}

C_OUT

C_FB

2 × (10-µF, 50-V ceramic) + 33-µF, 50-V electrolytic

15 pF

1 µF, 10 V

24 kΩ

C_LDO

R_ISET

R_FSET

R1

210 kΩ

750 kΩ

130 kΩ

10 kΩ

R2

R3

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Inductor Selection

There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor

current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of

application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.

The saturation current must be greater than the sum of the maximum load current, and the worst case average-

to-peak inductor current. 方程式 4 shows the worst case conditions

I_OUTMAX

I_SAT

>

+ I_RIPPLE

For Boost

D‘

V_IN

x

V_OUT

(V_OUT- V_IN)

(2 x L x f)

Where I_RIPPLE

=

(V_OUTœ V_IN)

and D‘ = (1 - D)

Where D =

(V_OUT

)

(4)

• I_RIPPLE- peak inductor current

• I_OUTMAX- maximum load current

• V_IN- minimum input voltage in application

• L - min inductor value including worst case tolerances

• f - minimum switching frequency

• V_OUT- output voltage

• D - Duty Cycle for CCM Operation

As a result, the inductor should be selected according to the I_SAT. A more conservative and recommended

approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A

saturation current rating of at least 2.5 A is recommended for most applications. See 表 7-2 for recommended

inductance value for the different switching frequency ranges. The inductor’s resistance should be less than

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300 mΩ for good efficiency.

See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies. Power Stage

Designer™ Tool can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer.

8.2.1.2.2 Output Capacitor Selection

A ceramic capacitor with 2 × V_{MAX BOOST}or more voltage rating is recommended for the output capacitor. The

DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance

value selection. Capacitance recommendations for different switching frequencies are shown in 表 7-2. To

minimize audible noise of ceramic capacitors their physical size should typically be minimized.

8.2.1.2.3 Input Capacitor Selection

A ceramic capacitor with 2 × V_{IN MAX}or more voltage rating is recommended for the input capacitor. The DC-bias

effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value

selection. Capacitance recommendations for different boost switching frequencies are shown in 表 7-2.

8.2.1.2.4 LDO Output Capacitor

A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The

DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance

value selection. Typically a 1-µF capacitor is sufficient.

8.2.1.2.5 Diode

A Schottky diode should be used for the boost output diode. Do not use ordinary rectifier diodes because slow

switching speeds and long recovery times degrade the efficiency and the load regulation. Diode rating for peak

repetitive current should be greater than inductor peak current (up to 3 A) to ensure reliable operation in boost

mode. Average current rating should be greater than the maximum output current. Schottky diodes with a low

forward drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage

of the Schottky diode significantly larger than the output voltage.

8.2.1.3 Application Curves

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN=5V

VIN=8V

VIN=12V

VIN=16V

VIN=5V

VIN=8V

VIN=12V

VIN=16V

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

D001

Load 3 strings, 8 LEDs per string

ƒ_sw= 300 kHz, 33 μH

100 mA/string for V_IN= 12 V and V_IN= 16 V

60 mA/string for V_IN= 8 V

100 mA/string for V_IN= 12 V and V_IN= 16 V

60 mA/string for V_IN= 8 V

50 mA/string for V_IN= 5 V

图 8-2. Boost Efficiency

图 8-3. System Efficiency

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20ms/div

OUT1/OUT2/BOOST 10V/div

FAULT 2V/div

图 8-5. Open LED Fault

图 8-4. Typical Start-Up

8.2.2 SEPIC Mode Application

When LED string voltage can be above or below V_INvoltage, SEPIC configuration can be used. In this example,

two separate coils are used for SEPIC. This can enable lower height external components to be used, compared

to a coupled coil solution. On the other hand, coupled coil typically maximizes the efficiency. Also, in this

example, an external clock is used to synchronize SEPIC switching frequency. External clock input can be

modulated to spread switching frequency spectrum.

L2

VIN

4.5...30 V

D1

Up to 8.5 V

L1

C1

C

OUT

C_{IN SEPIC}

R2

R1

SW

FB

VIN

Up to 100 mA/string

C_LDO

C

IN

LDO

OUT1

OUT2

R_FSET

TPS61193

FSET

OUT3

BOOST SYNC

BRIGHTNESS

SYNC

PWM

EN

VDDIO/EN

FAULT

ISET

R3

GND

PGND

PAD

VDDIO

R_ISET

图 8-6. SEPIC Mode, 3 Strings, 100-mA/String Configuration

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8.2.2.1 Design Requirements

DESIGN PARAMETER

VALUE

V_INvoltage range

4.5 V – 30 V

LED string

3P2S LEDs (7.2 V)

LED string current

100 mA

Maxmum output voltage

10 V

SEPIC switching frequency

2.2 MHz

External sync for SEPIC

used

Spread spectrum

Internal spread spectrum disabled (external sync used)

L1, L2

C_IN

10 µH

10 µF 50 V

C_{IN SEPIC}

C1

2 × 10-µF, 50-V ceramic + 33 µF 50-V electrolytic

10-µF 50-V ceramic

C_OUT

C_LDO

R_ISET

R_FSET

R1

2 × 10-µF, 50-V ceramic + 33 µF 50-V electrolytic

1 µF, 10 V

24 kΩ

184 kΩ

130 kΩ

10 kΩ

R2

R3

8.2.2.2 Detailed Design Procedure

In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output

voltage. Because of this, the maximum sum of input and output voltage must be limited below 50 V. See 节

8.2.1.2 for general external component guidelines. Main differences of SEPIC compared to boost are described

below.

Power Stage Designer™ Tool can be used for modeling SEPIC behavior: http://www.ti.com/tool/powerstage-

designer. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing

DC/DC Converters Based on SEPIC Topology.

8.2.2.2.1 Inductor

In SEPIC mode, currents flowing through the coupled inductors or the two separate inductors L1 and L2 are the

input current and output current, respectively. Values can be calculated using Power Stage Designer™ Tool or

using equations in Designing DC/DC Converters Based on SEPIC Topology.

8.2.2.2.2 Diode

In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak

repetitive current should be greater than SW pin current limit (up to 3 A for transients) to ensure reliable

operation in boost mode. Average current rating should be greater than the maximum output current. Diode

voltage rating must be higher than sum of input and output voltages.

8.2.2.2.3 Capacitor C1

Ti recommends a ceramic capacitor with low ESR. Diode voltage rating must be higher than maximum input

voltage.

24

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8.2.2.3 Application Curves

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN=5V

VIN=12V

VIN=15V

VIN=5V

VIN=8V

VIN=12V

VIN=15V

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

D001

Load 100mA per string, 3 strings, 2 LEDs per string

ƒ_sw= 2.2 MHz

Load 100mA per string, 3 strings, 2 LEDs per string

ƒ_sw= 2.2 MHz

2 × 10 μH, IHLP2525BDER100M

图 8-7. SEPIC Efficiency

图 8-8. System Efficiency

9 Power Supply Recommendations

The resistance of the input supply rail must be low enough so that the input current transient does not cause too

high drop at TPS61193 VIN pin. If the input supply is connected by using long wires additional bulk capacitance

may be required in addition to the ceramic bypass capacitors in the V_INline.

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10 Layout

10.1 Layout Guidelines

图 10-1 is a layout recommendation for TPS61193 used to demonstrate the principles of a good layout. This

layout can be adapted to the actual application layout if or where possible. It is important that all boost

components are close to the chip, and the high current traces must be wide enough. By placing boost

components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This

way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must as

close as possible to the device.

Here are some main points to help the PCB layout work:

• Current loops need to be minimized:

– For low frequency the minimal current loop can be achieved by placing the boost components as close as

possible to the SW and PGND pins. Input and output capacitor grounds must be close to each other to

minimize current loop size.

– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High-frequency return currents find a route with minimum impedance, which is

the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the positive”current route in the ground plane, if the ground plane is intact

under the route.

• The GND plane must be intact under the high current boost traces to provide shortest possible return path

and smallest possible current loops for high frequencies.

• Current loops when the boost switch is conducting and not conducting must be on the same direction in

optimal case.

• Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating

inductor 180° changes current direction.

• Use separate power and noise-free grounds. Power ground is used for boost converter return current and

noise-free ground for more sensitive signals, such as LDO bypass capacitor grounding as well as grounding

the GND pin of the device.

• Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the

diode cathode.

• Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.

• Input and output capacitors require strong grounding (wide traces, many vias to GND plane).

• If two output capacitors are used they must have symmetrical layout to get both capacitors working ideally.

• Output ceramic capacitors have a DC-bias effect. If the output capacitance is too low, it can cause boost to

become unstable on some loads, and this increases EMI. DC-bias characteristics should be obtained from

the component manufacturer; they are not taken into account on component tolerance. TI recommends

X5R/X7R capacitors.

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10.2 Layout Example

VIN

1

2

20

19

18

17

16

15

14

LDO

NC

R_FSET

SW

3

FSET

4

VDDIO/EN

FAULT

PGND

FB

5

6

OUT1

OUT2

SYNC

PWM

VBOOST

7

8

13

12

NC

OUT3

GND

9

R_ISET

11

10

ISET

图 10-1. TPS61193 Boost Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

Power Stage Designer^™Tool can be used for both boost and SEPIC: http://www.ti.com/tool/powerstage-designer

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• SNVU491

• PowerPAD™ Thermally Enhanced Package

• Understanding Boost Power Stages in Switch Mode Power Supplies

• Designing DC-DC Converters Based on SEPIC Topology

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

Power Stage Designer^™is a trademark of TI.

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28

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PACKAGE MATERIALS INFORMATION

www.ti.com

18-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS61193PWPR

HTSSOP PWP

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 20

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TPS61193PWPR

2000

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	TPS61193PWPR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
包装说明：	HTSSOP,
Reach Compliance Code：	compliant
ECCN代码：	EAR99
Factory Lead Time：	6 weeks
风险等级：	1.71
接口集成电路类型：	LED DISPLAY DRIVER
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	6.5 mm
湿度敏感等级：	2
复用显示功能：	NO
功能数量：	1
区段数：	6
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
座面最大高度：	1.2 mm
最大供电电压：	45 V
最小供电电压：	4.5 V
标称供电电压：	12 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
宽度：	4.4 mm
最小 fmax：	0.02 MHz
Base Number Matches：	1

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