UCC28070
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SLUS794–NOVEMBER 2007
Current-Sense Transformer (CT) Issue(s) When Operating In DCM
To maintain low THD over a wide range of line and load, AND keep a simple circuit, requires that Continuous
Conduction Mode (CCM) be maintained in the boost inductor over that same wide range. This requirement arises
out of the following situation:
The trend in PFC toward high-ripple, low-inductance design to reduce magnetics size and cost results in early
onset of discontinuous conduction mode (DCM) at high-line and/or lighter loads. Ordinarily, DCM can be
averaged as well as CCM, however a side-effect of DCM in conjunction with CT use leads to waveform distortion
in the following manner.
During the dead-time of DCM, when the boost inductor current has discharged to zero, the high voltage stored
on the MOSFET's COSS begins to ring back reverse current through the boost inductor and hence necessarily
backwards through the CT.
This reverse inductor current through the CT drives a reverse magnetizing current through the CT's inductance
which subsequently adds to the VRS signal level during the next switching cycle on-time. This additional signal
level overstates the scaled inductor current to the Current Amplifier (CA) with respect to the VIMO reference and
the CA acts to reduce the duty-cycle, thus maintaining and reinforcing the DCM. So it is a positive feedback
situation whereby DCM is artificially maintained along substantial portions of the lower sinewave, until VIN
becomes high enough to instigate CCM. Once in CCM, the current waveform faithfully follows VIMO until DCM
begins again some time after the peak of VIN.
For a given power level and input voltage, an ideal current sinewave can be calculated. The regions of inductor
DCM have less actual current than the ideal sinewave requires, and so VAO voltage increases VIMO to inflate the
CCM portion to compensate for the difference. Hence a significant amount of distortion can result from a small
amount of DCM.
The simplest way to avoid this is to design the inductance high enough to avoid DCM under all conditions where
low THD is required. Otherwise, additional compensating circuitry will be necessary to mitigate the DCM
situation, with complexity increasing as low-THD conditions are expanded.
To maintain <5% THD over 85 V-265 VRMS at full load only,
•
•
Design LB to avoid DCM up to 250 V-260 VRMS, and
Add a positive bias current injection circuit to VCSA and VCSB, which activates only at low-line (below ~155
VRMS). Bias current is adjusted empirically.
This is crude, fairly simple, and effective, but works only for full-load. The fixed bias current optimized for full load
is insufficient for lighter loads.
At lighter loads (say to 50%), one can follow the same method as above, with yet larger LB, or employ additional,
more complicated compensation techniques with variable bias levels and polarities under different conditions.
Ultimately, all compensation techniques are attempts to remove the influence of negative or positive magnetizing
current (iM) of the CT from the VRS signal. A fixed bias current has limited success in canceling a variable iM, and
more sophisticated adaptable bias-adjusting circuits are obviously more complicated and expensive.
Adjusting the switching period (TSW) by manipulating the values of RT and RDMX can be another technique, with
the objective to maintain CCM over more of the range of possible operating conditions. This can be effective as
long as variable switching frequency is permissible.
Also, low-loss resistive sensing can replace the CT if very wide GBW operational amplifiers are available. But
drawbacks of this approach include cost, complexity, leading-edge spikes (from gate drive), etc.
References
1. O’Loughlin, Michael, “An Interleaving PFC Pre-Regulator for High-Power Converters”, Texas Instruments,
Inc. 2006 Unitrode Power Supply Seminar, Topic 5
2. Erickson, Robert W., “Fundamentals of Power Electronics”, 1st ed., pp. 604-608 Norwell, MA: Kluwer
Academic Publishers, 1997
3. Creel, Kirby “Measuring Transformer Distributed Capacitance”, White Paper, Datatronic Distribution, Inc.
website: http://www.datatronics.com/pdf/distributed_capacitance_paper.pdf
Copyright © 2007, Texas Instruments Incorporated
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