UCC28070PWR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

UCC28070

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SLUS794–NOVEMBER 2007

Two-Phase Interleaved CCM PFC Controller

1

FEATURES

APPLICATIONS

•

High-Efficiency Server and Desktop Power

Supplies

•

Interleaved Average Current-Mode PWM

Control with Inherent Current Matching

•

Telecom Rectifiers

•

Advanced Current Synthesizer Current

Sensing for Superior Efficiency and PF

DESCRIPTION

Highly-Linear Multiplier Output with Internal

Quantized Voltage Feed-Forward Correction

for Near-Unity PF

The UCC28070 is an advanced power factor

correction device that integrates two pulse-width

modulators (PWMs) operating 180° out of phase.

This Natural Interleaved PWM operation generates

substantial reduction in the input and output ripple

currents, and the conducted-EMI filtering becomes

easier and less expensive. A significantly improved

multiplier design provides a shared current reference

to two independent current amplifiers that ensures

matched average current mode control in both PWM

outputs while maintaining a stable, low-distortion

sinusoidal input line current.

•

Programmable Frequency (up to 300 kHz)

Programmable Maximum Duty-Cycle Clamp

Programmable Frequency Dithering Rate and

Magnitude for Enhanced EMI Reduction

–

Magnitude: Up to 30 kHz

Rate: Up to 30 kHz

•

External Clock Synchronization Capability

Enhanced Load and Line Transient Response

through Voltage Amplifier Output Slew-Rate

Correction

The UCC28070 contains multiple innovations

including current synthesis and quantized voltage

feed-forward to promote performance enhancements

in PF, efficiency, THD, and transient response.

Features including frequency dithering, clock

synchronization, and slew rate enhancement further

expand the potential performance enhancements.

•

Programmable Peak Current Limiting

Bias-Supply UVLO, Over-Voltage Protection,

Open-Loop Detection, and PFC-Enable

Monitoring

•

External PFC-Disable Interface

The UCC28070 also contains a variety of protection

features including output over-voltage detection,

programmable peak-current limit, in-rush current

detection, under-voltage lockout, and open-loop

protection.

Open-Circuit Protection on VSENSE and

VINAC pins

•

Programmable Soft Start

20-Lead TSSOP Package

Typical Application Diagram

V_IN

L1

D1

V_OUT

C_OUT

12V to 21V

To CSB

C_CDR

T1

1

2

3

4

5

6

7

8

9

CDR

RDM

VAO

DMAX 20

RT 19

R_S

R_DMX

R_RT

R_RDM

R_A

SS 18

C_SS

M1

VSENSE GDB 17

VINAC

IMO

GND 16

VCC 15

R_IMO

R_SYN

R_B

RSYNTH GDA 14

L2

D2

CSB

CSA

VREF 13

CAOA 12

To CSA

10 PKLMT CAOB 11

T2

R_S

From Ixfrms

R_A

C_ZV

C_ZC

R_PK1

C_REF

C_PV

C_PC

M2

R_PK2

R_B

R_ZV

R_ZC

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

UCC28070

www.ti.com

SLUS794–NOVEMBER 2007

ORDERING INFORMATION

PART NUMBER

PACKAGE

PACKING

UCC28070PW

Plastic, 20-Pin TSSOP (PW)

70-Pc. Tube

UCC28070PWR

2000-Pc. Tape and Reel

ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)(4)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Supply voltage: VCC

LIMIT

22

UNIT

V

mA

V

Supply current: I_VCC

20

Voltage: GDA, GDB

−0.5 to VCC+0.3

+/− 0.25

+/− 0.75

Gate drive current – continuous: GDA, GDB

Gate drive current – pulsed: GDA, GDB

A

V

Voltage: DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA, CSB,

CAOA, CAOB, PKLMT, VREF

−0.5 to +7

Current: RT, DMAX, RDM, RSYNTH

Current: VREF, VAO, CAOA, CAOB, IMO

Operating junction temperature, T_J

Storage temperature, T_STG

−0.5

10

mA

−40 to +125

−65 to +150

260

°C

Lead temperature (10 seconds)

(1) These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at

these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to

absolute maximum rated conditions for extended periods of time may affect device reliability.

(2) All voltages are with respect to GND.

(3) All currents are positive into the terminal, negative out of the terminal.

(4) In normal use, terminals GDA and GDB are connected to an external gate driver and are internally limited in output current.

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

RATING

2,000

500

UNIT

Human Body Model (HBM)

V

Charged Device Model (CDM)

DISSIPATION RATINGS

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T_A= 25°C POWER

PACKAGE

T_A= 85°C POWER RATING

RATING

(2)

(1)

20-Pin TSSOP

125 °C/Watt ⁽¹⁾and

800 mW

320 mW

(1) Thermal resistance is a strong function of board construction and layout. Air flow reduces thermal resistance. This number is only a

general guide.

(2) Thermal resistance calculated with a low-K methodology.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

VCC Input Voltage (from a low-impedance source)

VREF Load Current

MIN

MAX

UNIT

V

V_UVLO+ 1 V

21

2

mA

VINAC Input Voltage Range

0

3

IMO Voltage Range

3.3

3.7

750

330

V

PKLMT, CSA, & CSB Voltage Range

0

RSYNTH Resistance (R_SYN

)

15

30

kΩ

RDM Resistance (R_RDM

)

2

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range −40°C < T_A< 125°C, T_J= T_A, VCC = 12 V, GND = 0 V, R_RT= 75 kΩ, R_DMX= 67.5

kΩ, R_RDM= R_SYN= 100 kΩ, R_IMO= 16 kΩ, C_CDR= 625 pF, C_SS= C_VREF= 0.1 µF, C_VCC= 1 µF, (unless otherwise noted)

SYMBOL

Bias Supply

VCC_SHUNT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

(1)

VCC shunt voltage

I_VCC= 10 mA

21

23

25

V

VCC current, disabled

VCC current, enabled

VSENSE = 0 V

7

8

mA

VSENSE = 3 V (no switching)

VCC = 7 V

TBD

100

µA

VCC current, UVLO

VCC = 9 V

4

10.2

1

TBD

10.6

mA

V_UVLO

UVLO turn-on threshold

UVLO hysteresis

Measured at VCC (rising)

Measured at VCC (falling)

Measured at VCC (rising)

9.8

V

VREF enable threshold

TBD

8

TBD

Linear Regulator

VREF voltage, no load

I_VREF= 0 mA

5.9

5.8

5.9

6

6.1

VREF voltage, full load

VREF voltage, over line

I_VREF= −2 mA

11 V < VCC < 20 V, I_REF= 0 mA

PFC Enable

V_EN

Enable threshold

Enable hysteresis

Measured at VSENSE (rising)

0.65

TBD

0.75

0.15

0.85

V

External PFC Disable

Disable threshold

Measured at SS (falling)

VSENSE > 0.85 V

0.6

Hysteresis

0.15

Oscillator

Output phase shift

Measured between GDA and GDB

Measured at DMAX, RT, & RDM

180

3

TBD Degree

V

V_DMAX,V_RT

and V_RDM

,

Timing regulation voltages

R_RT= 250 kΩ, R_DMX= 225 kΩ,

V_RDM= 0 V, V_CDR= 6 V

27

270

30

300

95%

133

33

kHz

330

f_PWM

PWM switching frequency

R_RT= 25 kΩ, R_DMX= 22.5 kΩ,

V_RDM= 0 V, V_CDR= 6 V

R_RT= 75 kΩ, R_DMX= 67.5 kΩ,

V_RDM= 0 V, V_CDR= 6 V

D_MAX

Duty-cycle clamp

TBD%

TBD

TBD%

TBD

R_RT= 25 kΩ, R_DMX= 22.5 kΩ,

V_RDM= 0 V, V_CDR= 6 V

Minimum programmable off-time

ns

Frequency dithering magnitude

Change in f_PWM

R_RDM= 313 kΩ, R_RT= 75 kΩ

R_RDM= 31 kΩ, R_RT= 25 kΩ

C_CDR= 2.2 nF, R_RDM= 100 kΩ

C_CDR= 0.22 nF, R_RDM= 100 kΩ

Measure at CDR (sink and source)

Measured at C_CDR(rising)

2.5

27

3

30

3

3.5

33

f_DM

kHz

Frequency dithering rate

Rate of change in f_PWM

Dither rate current

f_DR

30

10

5

µA

I_CDR

Dither disable threshold

TBD

V

(1) Excessive VCC input voltage and/or current damages the device. This clamp will not protect the device from an unregulated supply. If

an unregulated supply is used, a series-connected fixed positive voltage regulator such as a UA78L15A is recommended. See the

Absolute Maximum Ratings section for the limits on VCC voltage and current.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range −40°C < T_A< 125°C, T_J= T_A, VCC = 12 V, GND = 0 V, R_RT= 75 kΩ, R_DMX= 67.5

kΩ, R_RDM= R_SYN= 100 kΩ, R_IMO= 16 kΩ, C_CDR= 625 pF, C_SS= C_VREF= 0.1 µF, C_VCC= 1 µF, (unless otherwise noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Clock Synchronization

V_CDR

SYNC enable threshold

Measured at CDR (rising)

5

TBD

V

V_CDR= 6 V, Measured from RDM (rising) to

GDx (rising)

SYNC propagation delay

50

TBD

1.5

ns

SYNC threshold (Rising)

SYNC threshold (Falling)

V_CDR= 6 V, Measured at RDM (rising)

V_CDR= 6 V, Measured at RDM (falling)

Positive pulse width

1.2

0.7

V

0.4

0.2

µs

SYNC pulses

(2)

Maximum duty cycle

75

%

Voltage Amplifier

VSENSE voltage

In regulation, T_A= 25°C

In regulation

2.97

2.94

3

3.03

3.06

TBD

5.2

V

nA

V

VSENSE voltage

VSENSE input bias current

VAO high voltage

In regulation

250

5

VSENSE = 2.9 V

4.8

VAO low voltage

VSENSE = 3.1 V

0.05

70

TBD

g_MV

VAO transconductance

VAO sink current, overdriven limit

VAO source current, overdriven

2.8 V < VSENSE < 3.2 V, VAO = 3 V

VSENSE = 3.5 V, VAO = 3 V

VSENSE = 2.5 V, VAO = 3 V, SS = 3 V

µS

30

−30

µA

VAO source current,

overdriven limit + I_SRC

VSENSE = 2.5 V, VAO = 3 V

−130

Measured as VSENSE (falling) / VSENSE

(regulation)

Slew-rate correction threshold

Slew-rate correction hysteresis

Slew-rate correction current

92

93

6

95

%

Measured at VSENSE (rising)

TBD

mV

µA

Measured at VAO, in addition to VAO

source current.

I_SRC

−100

Slew-rate correction enable threshold

VAO discharge current

Measured at SS (rising)

4

V

VSENSE = 0.5 V, VAO = 1 V

10

µA

Soft Start

I_SS

SS source current

Adaptive source current

Adaptive SS disable

SS sink current

VSENSE = 0.9 V, SS = 1 V

VSENSE = 1.1 V, SS = 1 V

Measured as VSENSE – SS

VSENSE = 0.5 V, SS = 0.2 V

−10

−1

0

µA

mA

mV

mA

0.5

0.9

(2) Due to the programmability of the maximum PWM switching duty cycle (D_MAX), the maximum duty cycle of a synchronization pulse must

be reasonably (~5-10%) less than 2 x D_MAX-1.

4

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range −40°C < T_A< 125°C, T_J= T_A, VCC = 12 V, GND = 0 V, R_RT= 75 kΩ, R_DMX= 67.5

kΩ, R_RDM= R_SYN= 100 kΩ, R_IMO= 16 kΩ, C_CDR= 625 pF, C_SS= C_VREF= 0.1 µF, C_VCC= 1 µF, (unless otherwise noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Over Voltage

Measured as VSENSE (rising) / VSENSE

(regulation)

V_OVP

OVP threshold

104

106

108

%

mV

µs

OVP hysteresis

Measured at VSENSE (falling)

100

Measured between VSENSE (rising) and

GDx (falling)

OVP propagation delay

TBD

0.5

Zero-Power

V_ZPWR

Zero-power detect threshold

Zero-power hysteresis

Measured at VAO (falling)

TBD

0.75

0.15

V

Multiplier

VAO > 1.5 V

16

15

17

0

18

19

k_MULT

Gain constant

µA

VAO = 1.2 V

VINAC = 0.9 V_PK, VAO = 0.8 V

VINAC = 0 V, VAO = 5 V

-0.2

0.2

I_IMO

Output current: zero

0

Quantized Voltage Feed Forward

(3)

V_LVL1

V_LVL2

V_LVL3

V_LVL4

V_LVL5

V_LVL6

V_LVL7

V_LVL8

Level 1 threshold

Level 2 threshold

Level 3 threshold

Level 4 threshold

Level 5 threshold

Level 6 threshold

Level 7 threshold

Level 8 threshold

0.6

0.7

1

0.8

1.2

1.4

Measured at VINAC (rising)

V

1.65

1.95

2.25

2.6

Current Amplifiers

CAOx high voltage

TBD

6

TBD

100

50

V

µS

µA

V

CAOx low voltage

0.1

g_MC

CAOx transconductance

CAOx sink current, overdriven

CAOx source current, overdriven

Input common mode range

Input offset voltage

−50

0

3.6

IMO = 0 V

−1

−3

0

−5

mV

Measured as Phase A’s input offset minus

Phase B’s input offset

Phase mismatch

TBD

0.5

TBD

CAOx pull-down current

VSENSE = 0.5 V, CAOx = 0.2 V

0.9

mA

(3) The Level 1 threshold represents the “zero-crossing detection” threshold above which VINAC must rise to initiate a new input half-cycle,

and below which VINAC must fall to terminate that half-cycle.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range −40°C < T_A< 125°C, T_J= T_A, VCC = 12 V, GND = 0 V, R_RT= 75 kΩ, R_DMX= 67.5

kΩ, R_RDM= R_SYN= 100 kΩ, R_IMO= 16 kΩ, C_CDR= 625 pF, C_SS= C_VREF= 0.1 µF, C_VCC= 1 µF, (unless otherwise noted)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Current Synthesizer

VSENSE = 3 V, VINAC = 0 V

VSENSE = 3 V, VINAC = 2.85 V

Measured at RSYNTH (rising)

3

V_RSYNTH

Regulation voltage

0.15

5

V

Synthesizer disable threshold

VINAC input bias current

TBD

250

TBD

nA

Peak Current Limit

Peak current limit threshold

PKLMT = 3.30 V, measured at CSx (rising)

3.27

3.3

3.33

100

V

Measured between CSx (rising) and GDx

(falling) edges

Peak current limit propagation delay

TBD

ns

PWM Ramp

V_RMP

PWM ramp amplitude

4

V

PWM ramp offset voltage

T_A= 25°C, R_RT= 75 kΩ

TBD

0.7

TBD

PWM ramp offset temperature

coefficient

−2

mV/ °C

In-Rush Current Detection

In-rush detection threshold

Measured as VSENSE - VINAC

VCC = 20 V, C_LOAD= 1 nF

0

mV

V

In-rush detection hyst.

20

Gate Drive

GDA, GDB output voltage, high,

clamped

11.5

10

13

15

GDA, GDB output voltage, High

GDA, GDB output voltage, Low

Rise time GDx

C_LOAD= 1 nF

10.5

0.2

18

11.5

0.3

30

25

2

C_LOAD= 1 nF

1 V to 9 V, C_LOAD= 1 nF

9 V to 1 V, C_LOAD= 1 nF

VCC = 0 V, I_GDA, I_GDB= 2.5 mA

ns

V

Fall time GDx

12

GDA, GDB output voltage, UVLO

1.6

Thermal Shutdown

Thermal shutdown threshold

160

140

°C

Thermal shutdown recovery

DEVICE INFORMATION

TSSOP-20 Top View, PW Package

CDR

RDM

20 DMAX

19 RT

1

2

3

4

5

6

7

8

9

VAO

18 SS

VSENSE

VINAC

IMO

17 GDB

16 GND

15 VCC

14 GDA

13 VREF

RSYNTH

CSB

CSA

CAOA

12

PKLMT 10

11 CAOB

6

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TERMINAL FUNCTIONS

NAME

PIN #

I/O

DESCRIPTION

Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs

the rate of oscillator dither. Connect the CDR pin to the VREF pin to disable dithering.

CDR

1

I

Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An

external resistor to GND programs the magnitude of oscillator frequency dither. When frequency

dithering is disabled (CDR > 5 V), the internal master clock will synchronize to positive edges

presented on the RDM pin. Connect RDM to GND when dithering is disabled and synchronization

is not desired.

RDM

(SYNC)

2

I

Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally

connected to Multiplier input and Zero-Power comparator. Connect the voltage regulation loop

compensation components between this pin and GND.

VAO

3

4

5

O

I

Output Voltage Sense. Internally connected to the inverting input of the transconductance

voltage error amplifier in addition to the positive terminal of the Current Synthesis difference

amplifier. Also connected to the OVP, PFC Enable, and slew-rate comparators. Connect to PFC

output with a resistor-divider network.

VSENSE

VINAC

Scaled AC Line Input Voltage. Internally connected to the Multiplier and negative terminal of the

Current Synthesis difference amplifier. Connect a resistor-divider network between V_IN, VINAC,

and GND identical to the PFC output divider network connected at VSENSE.

I

Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier

gain.

IMO

RSYNTH

CSB

6

7

8

9

O

I

Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to

set the magnitude of the current synthesizer down-slope.

Phase B Current Sense Input. During the on-time of GDB, CSB is internally connected to the

inverting input of Phase B’s current amplifier.

I

Phase A Current Sense Input. During the on-time of GDA, CSA is internally connected to the

inverting input of Phase A’s current amplifier.

CSA

I

Peak Current Limit Programming. Connect a resistor-divider network between VREF and this

PKLMT

CAOB

10

11

I

pin to set the voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows

adjustment for desired ΔI_LB

.

Phase B Current Amplifier Output. Output of phase B’s transconductance current amplifier.

Internally connected to the inverting input of phase B’s PWM comparator for trailing-edge

modulation. Connect the current regulation loop compensation components between this pin and

GND.

O

Phase A Current Amplifier Output. Output of phase A’s transconductance current amplifier.

Internally connected to the inverting input of phase A’s PWM comparator for trailing-edge

modulation. Connect the current regulation loop compensation components between this pin and

GND.

CAOA

12

O

6-V Reference Voltage and Internal Bias Voltage. Connect a 0.1-µF ceramic bypass capacitor

as close as possible to this pin and GND.

VREF

GDA

VCC

GND

13

14

15

16

O

Phase A’s Gate Drive. This limited-current output is intended to connect to a separate gate-drive

device suitable for driving the Phase A switching component(s). The output voltage is typically

clamped to 13.5 V.

Bias Voltage Input. Connect a 0.1-µF ceramic bypass capacitor as close as possible to this pin

and GND.

I

Device Ground Reference. Connect all compensation and programming resistor and capacitor

networks to this pin. Connect this pin to the system through a separate trace for high-current

noise isolation.

I/O

Phase B’s Gate Drive. This limited-current output is intended to connect to a separate

gate-drivedevice suitable for driving the Phase B switching component(s). The output voltage is

typically clamped to 13.5 V.

GDB

SS

17

18

O

I

Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the

soft-start slew rate based on an internally-fixed 10-µA current source. The regulation reference

voltage for VSENSE is clamped to V_SSuntil V_SSexceeds 3 V. Upon recovery from certain fault

conditions a 1-mA current source is present at the SS pin until the SS voltage equals the

VSENSE voltage. Pulling the SS pin below 0.6 V immediately disables both GDA and GDB

outputs.

Timing Resistor. Oscillator frequency programming pin. A resistor to GND sets the running

frequency of the internal oscillator.

RT

19

20

I

Maximum Duty-Cycle Resistor. Maximum PWM duty-cycle programming pin. A resistor to GND

DMAX

sets the PWM maximum duty-cycle based on the ratio of R_DMX/R_RT

.

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Functional Block Diagram

VINAC

+

In-Rush

20mV Hys.

VCC 15

Fault

20mV

23V

VSENSE

ReStart

Ext. Disable

o

160 On

140 Off

ThermSD

3.18V

C

+

Linear

EN

3.08V

6V

VREF 13

Regulator

8V

0.75V

0.60V

S

R

Q

0.75V

0.60V

OVP

+

SS

VSENSE

0.90V

0.75V

GND 16

+

UVLO

ZeroPwr

10.2V

9.2V

VAO

6

5

IMO

VINAC

20

19

Voltage

Feed-

DMAX

RT

250nA

CLKA

CLKB

OffA

Forward

V

_VINAC* (V_VAO– 1)

Oscillator w/

Freq. Dither

I_IMO

=

* 17uA

K_VFF

x

/

OffB

Mult.

x

3

VAO

SS

4V

+

ReStart

RDM/

SYNC

Logic

2

1

100uA

5V

Slew Rate

Correction

2.8V

SYNC

Dither

+

10uA

Enable Disable

+

CDR

5V

Gm Amp

-

4

VSENSE

+

3V

VA

250nA

+

Adaptive SS

10

PKLMT

+

1mA

IpeakA

ReStart

ISS

10uA

+

Control

Logic

ReStart

Ext. Disable

IpeakB

9

CSA

+

18 SS

PWM1

+

CA1

VCC

Gm Amp

+

S

R

Q

(Clamped at 13.5V)

Driver 14

GND

OutA

OffA

IpeakA

GDA

CLKA

CSB

8

7

OutB

Current

Synthesizer

Fault

PWM2

RSYNTH

Disable

+

CA2

VCC

(Clamped at 13.5V)

+

VINAC

S

R

Q

Gm Amp

+

5V

VSENSE

OffB

CLKB

Driver

17

GDB

IpeakB

12

11

CAOA

CAOB

Fault

GND

8

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APPLICATION INFORMATION

THEORY OF OPERATION

Natural Interleaving

One of the main benefits from the natural interleaving of phases is significant reductions in the high-frequency

ripple components of both the input current and the current into the output capacitor of the PFC pre-regulator.

Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the

burden of filtering conducted-EMI noise and helps reduce the EMI filter and C_INsizes. Additionally, reduced

high-frequency ripple current into the PFC output capacitor, C_OUT, helps to reduce its size and cost. Furthermore,

with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a

single-phase design [1].

Ripple current reduction due to interleaving is often referred to as “ripple cancellation”, but strictly speaking, the

peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other

than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual

phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC pre-regulator,

those of a 2-phase naturally-interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation,

the frequency of the naturally-interleaved ripple, at both the input and output, is 2 x f_PWM

.

On the input, natural interleaving reduces the peak-to-peak ripple amplitude to 1/2 or less of the ripple amplitude

of the equivalent single-phase current.

On the output, Natural Interleaving reduces the rms value of the PFC-generated ripple current in the output

capacitor by a factor of slightly more than √2, for PWM duty-cycles > 50% as derived from following Erickson’s

method [2].

Programming the PWM Frequency and Maximum Duty-Cycle Clamp

The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through

the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor

(R_RT) directly sets the PWM frequency (f_PWM).

7500

R_RTkW =

( )

f_PWMkHz

( )

Once R_RThas been determined, the D_MAXresistor (R_DMX) may be derived.

R_DMX= R ´ 2´ D

(

-1

)

RT

MAX

where D_MAXis the desired maximum PWM duty-cycle.

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Frequency Dithering (Magnitude and Rate)

Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise

beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which

results in equal time spent at every point along the switching frequency range. This total range from minimum to

maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency

f_PWMset with R_RT. For example, a dither magnitude of 20 kHz on a nominal f_PWMof 100 kHz results in a

frequency range of 100 kHz ±10 kHz. Furthermore, the programmed duty-cycle clamp set by R_DMXremains

constant at the programmed value across the entire range of the frequency dithering.

The rate at which f_PWMtraverses from one extreme to the other and back again is defined as the dither rate. For

example, a dither rate of 1 kHz would linearly modulate the nominal frequency from 110 kHz to 90 kHz to 110

kHz once every millisecond. A good initial design target for dither magnitude is ±10% of f_PWM. Most boost

components can tolerate such a spread in f_PWM. The designer can then iterate around there to find the best

compromise between EMI reduction, component tolerances, and loop stability.

The desired dither magnitude is set by a resistor from the RDM pin to GND, of value calculated by the following

equation:

937.5

R_RDMkW =

( )

f_DMkHz

( )

Once the value of R_RDMis determined, the desired dither rate may be set by a capacitor from the CDR pin to

GND, of value calculated by the following equation:

æ

ç

è

ö

÷

ø

R_RDM

C_CDRpF = 66.7´

( )

kW / kHz

(

)

f_DR

Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and

connecting the RDM pin directly to GND. (If populated, the relatively high impedance of the RDM resistor may

allow system switching noise to couple in and interfere with the controller timing functions if not bypassed with a

low impedance path when dithering is disabled.)

If an external frequency source is used to synchronize f_PWMand frequency dithering is desired, the external

frequency source must provide the dither magnitude and rate functions as the internal dither circuitry is disabled

to prevent undesired performance during synchronization. (See SubSec2 0.1 section for more details.)

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External Clock Synchronization

The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By

disabling frequency dithering (pulling CDR > 5 V), the UCC28070’s SYNC circuitry is enabled permitting the

internal oscillator to be synchronized with pulses presented on the RDM pin. In order to ensure a precise 180

degree phase shift is maintained between the GDA and GDB outputs, the frequency (f_SYNC) of the pulses

presented at the RDM pin needs to be at twice the desired f_PWM. For example, if a 100-kHz switching frequency

is desired, the f_SYNCshould be 200 kHz.

In order to ensure the internal oscillator does not interfere with the SYNC function, R_RTshould be sized to set the

internal oscillator frequency at least 10% below the f_SYNC. It must be noted that the PWM modulator gain will be

reduced by a factor equivalent to the scaled R_RTdue to a direct correlation between the PWM ramp current and

R_RT. Adjustments to the current loops should be made accordingly.

The maximum duty-cycle clamp programmability is still maintained via the selection of R_DMXbased on the second

and third equations below.

f_SYNC

f_PWM

=

2

15000

R^'_RTkW =

( )

f_SYNCkHz

( )

R_DMXkW = R^'´ 2 ´ D

-1

MAX

( )

(

)

RT

15000

R_RTkW =1.1´

( )

f_SYNCkHz

( )

f_{SYN(maxD )}£ 0.9´ 2´ D

(

-1

)

MAX

NOTE:

When external synchronization is used, a propagation delay of approximately 50 ns to

100 ns exists between internal timing circuits and the SYNC signal’s rising edge,

which may result in reduced off-time at the highest of switching frequencies.

Therefore, R_DMXshould be adjusted downward slightly by (T_SYNC-0.1 µs)/T_SYNCto

compensate. At lower SYNC frequencies, this delay becomes an insignificant fraction

of the PWM period, and can be neglected.

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Multi-phase Operation

External synchronization also facilitates using more than 2 phases for interleaving. Multiple UCC28070s can

easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate

phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be

obtained. (An odd number of phases can be accommodated if desired, but the ripple cancellation would not be

optimal.) For 4-, 6-, or any 2 x n-phases (where n = the number of UCC28070 controllers), each controller should

receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application

interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation.

Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for

optimal ripple cancellation.

In a multi-phase interleaved system, each current loop is independent and treated separately, however there is

only one common voltage loop. To maintain a single control loop, all VSENSE, VINAC, SS, IMO and VAO

signals are paralleled, respectively between the n controllers. Where current-source outputs are combined (SS,

IMO, VAO), the calculated load impedances must be adjusted by 1/n to maintain the same performance as with

a single controller.

Figure 20 illustrates the paralleling of two controllers for a 4-phase 90°-interleaved PFC system.

VSENSE and VINAC Resistor Configuration

The primary purpose of the VSENSE input is to provide the voltage feedback from the output to the voltage

control loop. Thus, a traditional resistor-divider network needs to be sized and connected between the output

capacitor and the VSENSE pin to set the desired output voltage based on the 3-V regulation voltage on

VSENSE.

A unique aspect of the UCC28070 is the need to place the same resistor-divider network on the V_INside of the

inductor to the VINAC pin. This provides the scaled input voltage monitoring needed for the linear multiplier and

current synthesizer circuitry. It is not required that the actual resistance of the VINAC network be identical to the

VSENSE network, but it is necessary that the attenuation (k_R) of the two divider networks be equivalent for

proper PFC operation.

R_B

k_R=

R + R

(

)

A

B

In noisy environments, it may be beneficial for small filter capacitors to be applied to the VSENSE and VINAC

inputs to avoid the destabilizing effects of excessive noise on these inputs. If applied, the RC time-constant

should not exceed 100µs on the VSENSE input to avoid significant delay in the output transient response. The

RC time-constant should also not exceed 100 µs on the VINAC input to avoid degrading of the wave-shape

zero-crossings. Usually, a time constant of 3/f_PWMis adequate to filter out typical noise on VSENSE and VINAC.

Some design and test iteration may be required to find the optimal amount of filtering required in a particular

application.

VSENSE and VINAC Open Circuit Protection

Both the VSENSE and VINAC pins have been designed with an internal 250-nA current sink to ensure that in the

event of an open circuit at either pin, the voltage is not left undefined, and the UCC28070 remains in a “safe”

operating mode.

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VIN

L1

D1

–

+

To CSB1

R_DMX1

T1

R_S1

VREF1

1

2

3

4

5

6

7

8

9

CDR

RDM

VAO

DMAX 20

RT 19

R_RT1

SS 18

R_A

M1

VSENSE GDB 17

VINAC

IMO

GND 16

VCC 15

12V to 21V

R_B

RSYNTH GDA 14

L2

CSB1

From Ixfrms

CSA1

VREF1

D2

CSB

CSA

VREF 13

CAOA 12

To CSA1

10 PKLMT CAOB 11

T2

R_S2

M2

C_ZV

C_ZC

R_PK1

C_REF

C_PV

C_PC

C_SS

R_PK2

V_OUT

R_ZV

R_ZC

R_A

C_OUT

C_PC

R_B

C_REF

C_ZC

Vin

L3

D3

To CSA2

T3

R_S3

10 PKLMT CAOB 11

CSB2

9

8

7

6

5

4

3

2

1

CSA

CSB

CAOA 12

VREF 13

From Ixfrms

CSA2

VREF2

M3

RSYNTH GDA 14

12V to 21V

IMO

VCC 15

GND 16

VINAC

VSENSE GDB 17

L4

D4

VAO

RDM

CDR

SS 18

RT 19

R_RT2

To CSB2

DMAX 20

R_DMX

2

T4

Synchronized

Clocks

R_S4

w/ 180^o

Phase Shift

M4

Figure 20. Functional Four-Phase Application Schematic Using Two UCC28070

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Current Synthesizer

One of the most prominent innovations in the UCC28070 design is the current synthesizer circuitry that

synchronously monitors the instantaneous inductor current through a combination of on-time sampling and

off-time down-slope emulation.

During the on-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins

respectively via the current transformer network in each output phase. Meanwhile, the continuous monitoring of

the input and output voltage via the VINAC and VSENSE pins permits the UCC28070 to internally recreate the

inductor current’s down-slope during each output’s respective off-time. Through the selection of the RSYNTH

resistor (R_SYN), based on the equation below, the internal circuitry may be adjusted to accommodate the wide

range of inductances expected across the wide array of applications.

Waveform at

CSx input

Synthesized

down-slope

Current Synthesizer

output to CA

Figure 21. Inductor Current’s Down Slope

10´ N ´ L mH ´k

_B( )

(

)

CT

R

R_SYNkW =

( )

R W

_S( )

Variables

•

L_B= Nominal Boost Inductance (µH),

R_S= Sense Resistor (Ω),

N_CT= Current-sense Transformer turns ratio,

k_R= R_B/(R_A+R_B) = the resistor-divider attenuation at the VSENSE and VINAC pins.

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Programmable Peak Current Limit

The UCC28070 has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling

either GDA or GDB output whenever the corresponding current-sense input (CSA or CSB respectively) rises

above the voltage established on the PKLMT pin. Once an output has been disabled via the detection of peak

current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming

range of the PKLMT voltage extends to upwards of 4 V to permit the full utilization of the 3-V average current

sense signal range.

A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT,

provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. A load of

less than 0.5 mA is suggested, but if the resistance on PKLMT is very high, a small filter capacitor on PKLMT is

recommended to avoid operational problems in high-noise environments.

PKLMT

Externally Programmable Peak

10

Current Limit level (PKLMT)

IPEAKx

+

To Gate-Drive

Shut-down

CSx

Current

Synthesizer

To Current

Amplifier

DI

3V Average Current-sense

Signal Range, plus Ripple

Figure 22. Externally Programmable Peak Current Limit

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Linear Multiplier

The multiplier of the UCC28070 generates a reference current which represents the desired wave shape and

proportional amplitude of the ac input current. This current is converted to a reference voltage signal by the R_IMO

resistor, which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier

current is dependent upon the rectified, scaled input voltage V_VINACand the voltage-error amplifier output V_VAO

The V_VINACsignal conveys three pieces of information to the multiplier:

.

1. The overall wave-shape of the input voltage (typically sinusoidal),

2. the instantaneous input voltage magnitude at any point in the line cycle,

3. and the rms level of the input voltage.

The V_VAOsignal represents the total output power of the PFC pre-regulator.

A major innovation in the UCC28070 multiplier architecture is the internal quantized V_RMSfeed-forward (Q_VFF

)

circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow

response to transient line variations. A unique circuit algorithm detects the transition of the peak of V_VINAC

through seven thresholds and generates an equivalent VFF level centered within the eight Q_VFFranges. The

boundaries of the ranges expand with increasing V_INto maintain an approximately equal-percentage delta

between levels. These eight Q_VFFlevels are spaced to accommodate the full “universal” line range of 85 V-265

V_RMS

.

A great benefit of the Q_VFFarchitecture is that the fixed k_VFFfactors eliminate any contribution to distortion of the

multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion

components. Furthermore, the Q_VFFalgorithm allows for rapid response to both increasing and decreasing

changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in

the level thresholds help avoid “chattering” between Q_VFFlevels for V_VINACvoltage peaks near a particular

threshold or containing mild ringing or distortion. The Q_VFFarchitecture requires that the input voltage be largely

sinusoidal, and relies on detecting zero-crossings to adjust Q_VFFdownward on decreasing input voltage.

Zero-crossings are defined as V_VINACfalling below 0.7 V for at least 50 µs typically.

Table 1 reflects the relationship between the various VINAC peak voltages and the corresponding k_VFFterms for

the multiplier equation.

Table 1. VINAC Peak Voltages

(1)

LEVEL

V_VINACPEAK VOLTAGE

2.60 V ≤ V_VINAC(pk)

k_VFF(V²)

3.857

2.922

2.199

1.604

1.156

0.839

0.600

0.398

V_INPEAK VOLTAGE

> 345 V

8

7

6

5

4

3

2

1

2.25 V ≤ V_VINAC(pk)< 2.60 V

1.95 V ≤ V_VINAC(pk)< 2.25 V

1.65 V ≤ V_VINAC(pk)< 1.95 V

1.40 V ≤ V_VINAC(pk)< 1.65 V

1.20 V ≤ V_VINAC(pk)< 1.40 V

1.00 V ≤ V_VINAC(pk)< 1.20 V

300 V to 345 V

260 V to 300 V

220 V to 260 V

187 V to 220 V

160 V to 187 V

133 V to 160 V

< 133 V

V_VINAC(pk)≤ 1.00 V

(1) The V_INpeak voltage boundary values listed above are calculated based on a 400-V PFC output voltage and the use of a matched

resistor-divider network (k_R= 3 V/400 V = 0.0075) on VINAC and VSENSE (as required for current synthesis). When V_OUTis designed

to be higher or lower than 400 V, k_R= 3 V/V_OUT, and the V_INpeak voltage boundary values for each Q_VFFlevel adjust to V_VINAC(pk)/k_R.

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The multiplier output current I_IMOfor any line and load condition can thus be determined by the equation

17mA´ V

(

´ V -1

VAO

_VINAC) (

k_VFF

)

I_IMO

=

2

Because the k_VFFvalue represents the scaled V_RMSat the center of a level, V_VAOwill adjust slightly upwards or

downwards when VINAC_pkis either lower or higher than the center of the Q_VFFvoltage range to compensate for

the difference. This is automatically accomplished by the voltage loop control when V_INvaries, both within a level

and after a transition between levels.

The output of the voltage-error amplifier VAO is clamped at 5.0 V, which represents the maximum PFC output

power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the

maximum input power allowed (and, as a consequence, limits maximum output power).

Unlike a continuous V_FFsituation, where maximum input power is a fixed power at any V_RMSinput, the discrete

Q_VFFlevels permit a variation in maximum input power within limited boundaries as the input V_RMSvaries within

each level.

The lowest maximum power limit occurs at the VINAC voltage of 0.76 V, while the highest maximum power limit

occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold,

keeping in mind that decreasing thresholds are 95% of the increasing threshold values. Below VINAC = 0.76 V,

P_INis always less than P_IN(max), falling linearly to zero with decreasing input voltage.

For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average)

output power required of the PFC pre-regulator and add some additional percentage to account for line drop-out

recovery power (to recharge C_OUTwhile full load power is drawn) such as 10% or 20% of P_OUT(max). Then apply

the expected efficiency factor to find the lowest maximum input power allowable:

1.10´ P

OUT(max)

P

=

IN(max)

h

At the P_IN(max)design threshold, V_VINAC= 0.76 V, hence Q_VFF= 0.398 and input V_AC= 73 V_RMS(accounting for

2-V bridge-rectifier drop) for a nominal 400-V output system.

P

IN(max)

Thus I_{IN( rms )}

=

,and I_{IN( pk )}=1.414´ I_{IN( rms )}

73V_RMS

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This I_IN(pk)value represents the combined average current through the boost inductors at the peak of the line

voltage. Each inductor current is detected and scaled by a current-sense transformer (CT). Assuming equal

currents through each interleaved phase, the signal voltage at each current sense input pin (CSA and CSB) is

developed across a sense resistor selected to generate ~3 V based on (1/2) x I_IN(pk)x R_S/N_CT, where R_Sis the

burden current sense resistor and N_CTis the CT turns-ratio.

I_IMOis then calculated at that same lowest maximum-power point, as

0.76V 5V -1V

( )(

0.398

)

I_IMO(max)=17mA´

=130mA

R_IMOis selected such that:

1

æ ö

ç ÷

R_S

R_IMO´ I_IMO(max)

=

´ I_{IN( pk )}´

2

N_CT

è ø

Therefore:

æ 1

ç

ö

÷

ø

æ ö

ç ÷

´ I_{IN( pk )}´ R_S

2

è ø

è

R_IMO

=

N ´ I

(

)

CT

IMO(max)

At the increasing side of the level-1 to level-2 threshold, it should be noted that the IMO current would allow

much higher input currents at low-line:

1.0V 5V -1V

( )(

0.398

)

I_{IMO( L1-L2 )}=17mA´

=171mA

However, this current may easily be limited by the programmable peak current limiting (PKLMT) feature of the

UCC28070 if required by the power stage design.

The same procedure can be used to find the lowest and highest input power limits at each of the Q_VFFlevel

transition thresholds. At higher line voltages, where the average current with inductor ripple is traditionally below

the PKLMT threshold, the full variation of maximum input power will be seen, but the input currents will inherently

be below the maximum acceptable current levels of the power stage.

The performance of the multiplier in the UCC28070 has been significantly enhanced when compared to previous

generation PFC controllers, with high linearity and accuracy over most of the input ranges. The accuracy is at its

worst as V_VAOapproaches 1 V because the error of the (V_VAO-1) subtraction increases and begins to distort the

IMO reference current to a greater degree.

Enhanced Transient Response (VA Slew-Rate Correction)

Due to the low voltage loop bandwidth required to maintain proper PFC and ignore the slight 120-Hz ripple on

the output, the response of ordinary controllers to input voltage and load transients will also be slow. However,

the Q_VFFfunction effectively handles the line transient response with the exception of any minor adjustments

needed within a Q_VFFlevel. Load transients on the other hand can only be handled by the voltage loop, therefore,

the UCC28070 has been designed to improve its transient response by pulling up on the output of the voltage

amplifier (VAO) with an additional 100 µA of current in the event the VSENSE voltage drops below 93% of

regulation (2.79 V). During a soft-start cycle, when VSENSE is ramping up from the 0.75-V PFC Enable

threshold, the 100-µA correction current source is disabled to ensure the gradual and controlled ramping of

output voltage and current during a soft start.

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Voltage Biasing (VCC and VREF)

The UCC28070 operates within a VCC bias supply range of 10 V to 21 V. An Under-Voltage Lock-Out (UVLO)

threshold prevents the PFC from activating until VCC > 10.2 V, and 1 V of hysteresis assures reliable start-up

from a possibly low-compliance bias source. An internal 23-V zener-like clamp on VCC is intended only to protect

the device from brief energy-limited surges from the bias supply, and should NOT be used as a regulator with a

current-limited source.

At minimum, a 0.1-µF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to

provide local filtering of the bias supply. Larger values may be required depending on I_CCpeak current

magnitudes and durations to minimize ripple voltage on VCC.

In order to provide a smooth transition out of UVLO and to make the 6-V voltage reference available as early as

possible, the VREF output is enabled when VCC exceeds 8 V typically.

The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally.

At minimum, a 22-nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to

ensure stability of the circuit. External load current on VREF should be limited to less than 2 mA, or degraded

regulation may result.

PFC Enable and Disable

The UCC28070 contains two independent circuits dedicated to disabling the GDx outputs based on the biasing

conditions of the VSENSE or SS pins. The first circuit which monitors the V_VSENSE, is the traditional PFC Enable

that holds off soft-start and the overall PFC function until the output has pre-charged to ~25%. Prior to V_VSENSE

reaching 0.75 V, almost all of the internal circuitry is disabled. Once V_VSENSEreaches 0.75 V and VAO < 0.75 V,

the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage

on the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable

the GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6

V, the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present,

normal PWM operation resumes when the external SS pull-down is released. It must be noted that the external

pull-down needs to be sized large enough to override the internal 1-mA adaptive SS pull-up once the SS voltage

falls below the disable threshold. It is recommended that a MOSFET with less than 100-Ω R_DS(on)resistance be

used to ensure the SS pin is held adequately below the disable threshold.

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Adaptive Soft Start

In order to maintain a controlled power up, the UCC28070 has been designed with an adaptive soft-start function

that overrides the internal reference voltage with a controlled voltage ramp during power up. On initial power up,

once V_VSENSEexceeds the 0.75-V enable threshold (V_EN), the internal pull down on the SS pin is released, and

the 1-mA adaptive soft-start current source is activated. This 1-mA pull-up almost immediately pulls the SS pin to

0.75 V (V_VSENSE) to bypass the initial 25% of dead time during a traditional 0 V to Vregulation SS ramp. Once the

SS pin has reached the voltage on VSENSE, the 10-µA soft-start current (I_SS) takes over. Thus, through the

selection of the soft-start capacitor (C_SS), the effective soft-start time (t_SS) may be easily programmed based on

the equation below.

æ

ç

è

ö

÷

ø

2.25V

10mA

t_SS= C_SS´

Often, a system restart is desired following a brief shut-down. In such a case, VSENSE may still have substantial

voltage if V_OUThas not fully discharged or if high line has peak charged C_OUT. To eliminate the delay caused by

charging C_SSfrom 0 V up to the pre-charged V_VSENSEwith only the 10-µA current source and any further output

voltage sag, the adaptive soft start uses a 1-mA current source to rapidly charge C_SSto V_VSENSE, after which time

the 10-µA source controls the V_SSaccent to the desired soft-start ramp rate. In such a case, t_SSis estimated as

follows:

æ 3V -V_VSENSE0

ç

ö

÷

ø

t_SS= C_SS´

10mA

è

where V_VSENSE0is the voltage at VSENSE at the moment a soft start or restart is initiated.

(V)

V_SS

V_VSENSE

V_SSif no adaptive current

Time (s)

PFC externally

Reduced delay to regulation

disabled due to

AC-Line recovers

AC-line drop-out

and SS pin released

Figure 23. Soft-Start Ramp Rate

20

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PFC Start-Up Hold Off

An additional feature designed into the UCC28070 is the “Start-Up Hold Off” logic that prevents the device from

initiating a soft-start cycle until the VAO is below the zero-power threshold (0.75 V). This feature ensures that the

SS cycle will initiate from zero-power and zero duty-cycle while preventing the potential for any significant inrush

currents due to stored charge in the VAO compensation network.

Output Over-Voltage Protection (OVP)

Because of the high voltage output and a limited design margin on the output capacitor, output over-voltage

protection is essential for PFC circuits. The UCC28070 implements OVP through the continuous monitoring of

the VSENSE voltage. In the event V_VSENSErises above 106% of regulation (3.18 V), the GDx outputs are

immediately disabled to prevent the output voltage from reaching excessive levels. Meanwhile the CAOx outputs

are pulled low in order to ensure a controlled recovery starting from 0% duty-cycle after an OVP fault is released.

Once the V_VSENSEvoltage has dropped below 3.08 V, the PWM operation resumes normal operation.

Zero-Power Detection

In order to prevent undesired performance under no-load and near no-load conditions, the UCC28070

zero-power detection comparator is designed to disable both GDA and GDB output in the event the VAO voltage

falls below 0.75 V. The 150 mV of hysteresis ensures that the output remains disabled until the VAO has nearly

risen back into the linear range of the multiplier (VAO ≥ 0.9 V).

Thermal Shutdown

In order to protect the power supplies from silicon failures at excessive temperatures, the UCC28070 has an

internal temperature-sensing comparator that shuts down nearly all of the internal circuitry, and disables the GDA

and GDB outputs, if the die temperature rises above 160°C. Once the die temperature falls below 140°C, the

device brings the outputs up through a typical soft start.

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SLUS794–NOVEMBER 2007

Advanced Design Techniques

Current Loop Feedback Configuration

(Sizing of the Current Transformer Turns Ratio and Sense Resistor (R_S)

A current-sense transformer (C_T) is typically used in high-power applications to sense inductor current while

avoiding significant losses in the sensing resistor. For average current-mode control, the entire inductor current

waveform is required; however low-frequency CTs are obviously impracticable. Normally, two high-frequency

CTs are used, one in the switching leg to obtain the up-slope current and one in the diode leg to obtain the

down-slope current. These two current signals are summed together to form the entire inductor current, but this

is not the case for the UCC28070.

A major advantage of the UCC28070 design is the current synthesis function, which internally recreates the

inductor current down-slope during the switching period off-time. This eliminates the need for the diode-leg CT in

each phase, significantly reducing space, cost and complexity. A single resistor programs the synthesizer down

slope, as previously discussed in SubSec2 0.2 .

A number of trade-offs must be made in the selection of the CT. Various internal and external factors influence

the size, cost, performance, and distortion contribution of the CT.

These factors include, but are not limited to:

•

Turns-ratio (N_CT)

Magnetizing inductance (L_M)

Leakage inductance (L_LK)

Volt-microsecond product (Vµs)

Distributed capacitance (C_d)

Series resistance (R_SER

External diode drop (V_D)

External current sense resistor (R_S)

External reset network

)

Traditionally, the turns-ratio and the current sense resistor are selected first. Some iterations may be needed to

refine the selection once the other considerations are included.

22

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SLUS794–NOVEMBER 2007

In general, 50 ≤ N_CT≤ 200 is a reasonable range from which to choose. If N_CTis too low, there may be high

power loss in R_Sand insufficient L_M. If too high, there could be excessive L_LKand C_d. (A one-turn primary

winding is assumed.)

CSx

L_LK

R_SER

D

Reset

Network

I_DS

1

N_CT

L_Mi_M

C_d

R_S

Figure 28. Current Sense Transformer Equivalent Circuit

A major contributor to distortion of the input current is the effect of magnetizing current on the CT output signal

(i_RS). A higher turns-ratio results in a higher L_Mfor a given core size. L_Mshould be high enough that the

magnetizing current (i_M) generated is a very small percentage of the total transformed current. This is an

impossible criterion to maintain over the entire current range, because i_Munavoidably becomes a larger fraction

of i_RSas the input current decreases toward zero. The effect of i_Mis to “steal” some of the signal current away

from R_S, reducing the CSx voltage and effectively understating the actual current being sensed. At low currents,

this understatement can be significant and CAOx increases the current-loop duty-cycle in an attempt to correct

the CSx input(s) to match the IMO reference voltage. This unwanted correction results in overstated current on

the input wave shape in the regions where the CT understatement is significant, such as near the ac line zero

crossings. It can affect the entire waveform to some degree under the high line, light-load conditions.

The sense resistor R_Sis chosen, in conjunction with N_CT, to establish the sense voltage at CSx to be about 3 V

at the center of the reflected inductor ripple current under maximum load. The goal is to maximize the average

signal within the common-mode input range V_CMCAOof the CAOx current-error amplifiers, while leaving room for

the peaks of the ripple current within V_CMCAO. The design condition should be at the lowest maximum input power

limit as determined in the Multiplier Section. If the inductor ripple current is so high as to cause V_CSxto exceed

V_CMCAO, then R_Sor N_CTor both must be adjusted to reduce peak V_CSx, which could reduce the average sense

voltage center below 3 V. There is nothing wrong with this situation; but be aware that the signal is more

compressed between full- and no-load, with potentially more distortion at light loads.

The matter of volt-second balancing is important, especially with the widely varying duty-cycles in the PFC stage.

Ideally, the CT is reset once each switching period; that is, the off-time Vµs product equals the on-time Vµs

product. (Because a switching period is usually measured in microseconds, it is convenient to convert the

volt-second product to volt-microseconds to avoid sub-decimal numbers.) On-time Vµs is the time-integral of the

voltage across L_Mgenerated by the series elements R_SER, L_LK, D, and R_S. Off-time Vµs is the time-integral of the

voltage across the reset network during the off-time. With passive reset, Vµs-off is unlikely to exceed Vµs-on.

Sustained unbalance in the on or off Vµs products will lead to core saturation and a total loss of the

current-sense signal. Loss of V_CSxcauses V_CAOxto quickly rise to its maximum, programming a maximum

duty-cycle at any line condition. This, in turn causes the boost inductor current to increase without control, until

the system fuse or some component failure interrupts the input current.

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It is vital that the CT has plenty of Vµs design-margin to accommodate various special situations where there to

be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current

limiting.

Maximum Vµs(on) can be estimated by:

V_{m on max}= t_{ON max}´ V +V +V_RSER+V_LK

(

)

RS

D

( )

(

)

where all factors are maximized to account for worst-case transient conditions and t_ON(max)occurs during the

lowest dither frequency when frequency dithering is enabled. For design margin, a CT rating of ~5*Vµs(on)max

or higher is suggested. The contribution of V_RSvaries directly with the line current. However, V_Dmay have a

significant voltage even at near-zero current, so substantial Vµs(on) may accrue at the zero-crossings where the

duty-cycle is maximum. V_RSERis the least contributor, and often can be neglected if R_SER<<R_S. V_LKis developed

by the di/dt of the sensed current, and is not observable externally. However, its impact is considerable, given

the sub-microsecond rise-time of the current signal plus the slope of the inductor current. Fortunately, most of the

built-up Vµs across L_Mduring the on-time is removed during the fall-time at the end of the duty-cycle, leaving a

lower net Vµs(on) to be reset during the off-time. Nevertheless, the CT must, at the very minimum, be capable of

sustaining the full internal Vµs(on)max built up until the moment of turn-off within a switching period.

Vµs(off) may be generated with a resistor or zener diode, using the i_Mas bias current.

C_RST

D

R_RST

Z_RST

Figure 29. Possible Reset Networks

In order to accommodate various CT circuit designs and prevent the potentially destructive result due to CT

saturation, the UCC28070’s maximum duty-cycle needs to be programmed such that the resulting minimum

off-time accomplishes the required worst-case reset. (See the PWM Frequency and Duty-Cycle Clamp section of

the data sheet for more information on sizing R_DMX) Be aware that excessive C_din the CT can interfere with

effective resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT

self-resonant frequency. A higher turns-ratio results in higher C_d[3], so a trade-off between N_CTand D_MAXmust

be made.

The selected turns-ratio also affects L_Mand L_LK, which vary proportionally to the square of the turns. Higher L_Mis

good, while higher L_LKis not. If the voltage across L_Mduring the on-time is assumed to be constant (which it is

not, but close enough to simplify) then the magnetizing current is an increasing ramp.

This upward ramping current subtracts from i_RS, which affects V_CSxespecially heavily at the zero-crossings and

light loads, as stated earlier. With a reduced peak at V_CSx, the current synthesizer starts the down-slope at a

lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these

conditions. If low input current distortion at very light loads is required, special mitigation methods may need to

be developed to accomplish that goal.

24

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SLUS794–NOVEMBER 2007

Current-Sense Transformer (C_T) Issue(s) When Operating In DCM

To maintain low THD over a wide range of line and load, AND keep a simple circuit, requires that Continuous

Conduction Mode (CCM) be maintained in the boost inductor over that same wide range. This requirement arises

out of the following situation:

The trend in PFC toward high-ripple, low-inductance design to reduce magnetics size and cost results in early

onset of discontinuous conduction mode (DCM) at high-line and/or lighter loads. Ordinarily, DCM can be

averaged as well as CCM, however a side-effect of DCM in conjunction with CT use leads to waveform distortion

in the following manner.

During the dead-time of DCM, when the boost inductor current has discharged to zero, the high voltage stored

on the MOSFET's C_OSSbegins to ring back reverse current through the boost inductor and hence necessarily

backwards through the CT.

This reverse inductor current through the CT drives a reverse magnetizing current through the CT's inductance

which subsequently adds to the V_RSsignal level during the next switching cycle on-time. This additional signal

level overstates the scaled inductor current to the Current Amplifier (CA) with respect to the V_IMOreference and

the CA acts to reduce the duty-cycle, thus maintaining and reinforcing the DCM. So it is a positive feedback

situation whereby DCM is artificially maintained along substantial portions of the lower sinewave, until V_IN

becomes high enough to instigate CCM. Once in CCM, the current waveform faithfully follows V_IMOuntil DCM

begins again some time after the peak of V_IN.

For a given power level and input voltage, an ideal current sinewave can be calculated. The regions of inductor

DCM have less actual current than the ideal sinewave requires, and so VAO voltage increases V_IMOto inflate the

CCM portion to compensate for the difference. Hence a significant amount of distortion can result from a small

amount of DCM.

The simplest way to avoid this is to design the inductance high enough to avoid DCM under all conditions where

low THD is required. Otherwise, additional compensating circuitry will be necessary to mitigate the DCM

situation, with complexity increasing as low-THD conditions are expanded.

To maintain <5% THD over 85 V-265 V_RMSat full load only,

•

Design L_Bto avoid DCM up to 250 V-260 V_RMS, and

Add a positive bias current injection circuit to V_CSAand V_CSB, which activates only at low-line (below ~155

V_RMS). Bias current is adjusted empirically.

This is crude, fairly simple, and effective, but works only for full-load. The fixed bias current optimized for full load

is insufficient for lighter loads.

At lighter loads (say to 50%), one can follow the same method as above, with yet larger L_B, or employ additional,

more complicated compensation techniques with variable bias levels and polarities under different conditions.

Ultimately, all compensation techniques are attempts to remove the influence of negative or positive magnetizing

current (i_M) of the CT from the V_RSsignal. A fixed bias current has limited success in canceling a variable i_M, and

more sophisticated adaptable bias-adjusting circuits are obviously more complicated and expensive.

Adjusting the switching period (T_SW) by manipulating the values of R_Tand R_DMXcan be another technique, with

the objective to maintain CCM over more of the range of possible operating conditions. This can be effective as

long as variable switching frequency is permissible.

Also, low-loss resistive sensing can replace the CT if very wide GBW operational amplifiers are available. But

drawbacks of this approach include cost, complexity, leading-edge spikes (from gate drive), etc.

References

1. O’Loughlin, Michael, “An Interleaving PFC Pre-Regulator for High-Power Converters”, Texas Instruments,

Inc. 2006 Unitrode Power Supply Seminar, Topic 5

2. Erickson, Robert W., “Fundamentals of Power Electronics”, 1st ed., pp. 604-608 Norwell, MA: Kluwer

Academic Publishers, 1997

3. Creel, Kirby “Measuring Transformer Distributed Capacitance”, White Paper, Datatronic Distribution, Inc.

website: http://www.datatronics.com/pdf/distributed_capacitance_paper.pdf

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Product Folder Link(s): UCC28070

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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型号:	UCC28070PWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP20,.25
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	0.87
Is Samacsys：	N
模拟集成电路 - 其他类型：	POWER FACTOR CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	21 V
最小输入电压：	10.5 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	6.5 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	20
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	0.75 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	12 V
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Switching Regulator or Controllers
最大供电电流 (Isup)：	20 mA
最大供电电压 (Vsup)：	21 V
标称供电电压 (Vsup)：	12 V
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	330 kHz
技术：	BICMOS
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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