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产品型号USBUF01W6的概述

芯片USBUF01W6的概述 USBUF01W6是一款高性能单通道缓冲放大器，通常用于信号的缓冲和传输，其设计目标是为了提高信号的传输能力而对小信号进行放大。该芯片以其低功耗和高带宽的特性而受到广泛的应用，适用于各种电子设备中的模拟信号处理。芯片USBUF01W6的详细参数 USBUF01W6具有多个重要的电气参数，这些参数决定了它在不同应用场景中的有效性。以下是一些关键参数： - 工作电压范围：该芯片的工作电压通常在2.0V至5.5V之间，适合与多种电源兼容。 - 增益带宽积 (GBP)：USBUF01W6的增益带宽积通常为20MHz，表明其可以有效地处理高频信号。 - 输入失调电压：输入失调电压非常低，典型为0.5mV，可以保证信号的准确性。 - 输出驱动能力：该芯片能够提供高达600mA的输出电流，适合对负载要求较高的应用。 - 相位裕度：相位裕度较高，通常在60°以上，确保稳...

产品型号USBUF01W6的Datasheet PDF文件预览

USBUFxxW6

EMI FILTER AND LINE TERMINATION

FOR USB UPSTREAM PORTS

A.S.D.

APPLICATIONS

EMI Filter and line termination for USB upstream

ports on:

- USB Hubs

- PC peripherals

FEATURES

■

Monolithic device with recommended line termi-

nation for USB upstream ports

■

Integrated Rt series termination and Ct bypass-

ing capacitors.

■

Integrated ESD protection

Small package size

SOT323-6L

DESCRIPTION

The USB specification requires upstream ports

to be terminated with pull-up resistors from the

D+ and D- lines to Vbus. On the

implementation of USB systems, the radiated

and conducted EMI should be kept within the

required levels as stated by the FCC

regulations. In addition to the requirements of

termination and EMC compatibility, the

computing devices are required to be tested for

ESD susceptibility.

FUNCTIONAL DIAGRAM

3.3 V

The USBUFxxW6 provides the recommended line

termination while implementing a low pass filter to

limit EMI levels and providing ESD protection

which exceeds IEC61000-4-2 level 4 standard.

The device is packaged in a SOT323-6L which is

the smallest available lead frame package (50%

smaller than the standard SOT23).

Grd

3.3 V

BENEFITS

■

EMI / RFI noise suppression

■

Required line termination for USB upstream

ports

■

ESD protection exceeding IEC61000-4-2 level 4

High flexibility in the design of high density

boards

CODE 01

CODE 02

Tolerance

33Ω

22Ω

1.5kΩ

±10%

47pF

±20%

■

Tailored to meet USB 1.1 standard

±10%

TM: ASD and TRANSIL are a trademarks of STMicroelectronics.

March 2002 - Ed: 3A

1/9

USBUFxxW6

COMPLIES WITH THE FOLLOWING ESD

STANDARDS:

IEC61000-4-2, level 4

±15 kV (air discharge)

±8 kV (contact discharge)

MIL STD 883E, Method 3015-7

Class 3 C = 100 pF R = 1500 Ω

3 positive strikes and 3 negative strikes (F = 1 Hz)

ABSOLUTE RATINGS (T_amb= 25°C)

Symbol

Parameter

Value

Unit

V_PP

ESD discharge IEC 61000-4-2, air discharge

ESD discharge IEC 61000-4-2, contact discharge

ESD discharge - MIL STD 883E - Method 3015-7

±16

±9

±25

T_j

T_stg

T_L

Maximum junction temperature

Storage temperature range

150

- 55 to +150

260

°C

Lead solder temperature (10 second duration)

Operating temperature range

Power rating per resistor

°C

T_op

P_r

0 to 70

100

°C

TECHNICAL INFORMATION

Fig. A1: USB Standard requirements

3.3V

1.5k

D+

D-

D+

D-

Full-speed or

Low-speed USB

Transceiver

Full-speed USB

Transceiver

Twisted pair shielded

Zo = 90ohms

5m max

15k 15k

Hub 0 or

Host or

Full-speed function

Hub port

FULL SPEED CONNECTION

3.3V

1.5k

D+

D-

D+

D-

Full-speed or

Low-speed USB

Transceiver

Low-speed USB

Transceiver

Untwisted unshielded

3m max

15k 15k

Hub 0 or

Host or

Low-speed function

Hub port

LOW SPEED CONNECTION

2/9

USBUFxxW6

APPLICATION EXAMPLE

Fig. A2: Implementation of ST' solutions for USB ports

USBUF01W6

Upstream port

Downstream port

USBDF01W5

D+

Gnd

D+

CABLE

D+

D-

D+ in

Gnd

D+ out

D+

D-

Gnd

D-

3.3 V

D- in

D- out

D-

3.3V

FULL SPEED CONNECTION

USBUF01W6

Upstream port

Downstream port

USBDF01W5

D+

Gnd

D+

CABLE

D+

D+ in

Gnd

D+ out

D+

D-

Gnd

D-

3.3 V

D-

D- in

D- out

D-

3.3V

LOW SPEED CONNECTION

3/9

USBUFxxW6

EMI FILTERING

Current FCC regulations requires that class B computing devices meet specified maximum levels for both

radiated and conducted EMI.

- Radiated EMI covers the frequency range from 30MHz to 1GHz.

- Conducted EMI covers the 450kHz to 30MHz range.

For the types of devices utilizing the USB, the most difficult test to pass is usually the radiated EMI test. For

this reason the USBUFxxW6 device is aiming to minimize radiated EMI.

The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted

EMI because the magnetic field of both conductors cancels each other.

The inside of the PC environment is very noisy and designers must minimize noise coupling from the

different sources. D+ and D- must not be routed near high speed lines (clocks spikes).

Induced common mode noise can be minimized by running pairs of USB signals parallel to each other and

running grounded guard trace on each side of the signal pair from the USB controller to the USBUF device.

If possible, locate the USBUF device physically near the USB connectors. Distance between the USB con-

troller and the USB connector must be minimized.

The 47pF (Ct) capacitors are used to bypass high frequency energy to ground and for edge control, and

are placed between the driver chip and the series termination resistors (Rt). Both Ct and Rt should be

placed as close to the driver chip as is practicable.

The USBUFxxW6 ensures a filtering protection against ElectroMagnetic and RadioFrequency Interferences

thanks to its low-pass filter structure. This filter is characterized by the following parameters :

- cut-off frequency

- Insertion loss

- high frequency rejection.

Fig. A3: USBUFxxW6 typical attenuation curve.

Fig. A4: Measurement configuration

S21 (dB)

TEST BOARD

50Ω

-10

-20

-30

50Ω

100

1,000

Frequency (MHz)

ESD PROTECTION

In addition to the requirements of termination and EMC compatibility, computing devices are required to be

tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe.

This test requires that a device tolerates ESD events and remains operational without user intervention.

The USBUFxxW6 is particularly optimized to perform ESD protection. ESD protection is based on the use

of device which clamps at :

cl = VBR + R .IPP

This protection function is splitted in 2 stages. As shown in figure A5, the ESD strikes are clamped by the

first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor Rt.

Such a configuration makes the output voltage very low at the output.

4/9

USBUFxxW6

Fig. A5: USBUFxxW6 ESD clamping behavior

Vinput

Rload

V_PP

Voutput

V_BR

Device

to be

ESD Surge

USBUF01W6

protected

Fig. A6: Measurement board

ESD

SURGE

TEST BOARD

16kV

Air

Discharge

Vin

Vout

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and

Rload>Rd, it gives these formulas:

.VBR + R

.Vg

Vinput =

.VBR + R

.Vinput

Voutput =

The results of the calculation done for Vg=8kV, Rg=330Ω (IEC61000-4-2 standard), V_BR=7V (typ.)

and Rd = 1Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due

the low current involved after the resistance Rt.

The measurements done hereafter show very clearly (Fig. A7) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on Voutput stage

- Voutput clamping voltage very close to V_BR(breakdown voltage) in the positive way

and -V_F(forward voltage) in the negative way

5/9

USBUFxxW6

Fig. A7: Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge.

Vin

Vout

a. Positive surge

b.Negative surge

Please note that the USBUFxxW6 is not only acting for positive ESD surges but also for negative ones. For

these kinds of disturbances it clamps close to ground voltage as shown in Fig. A7b.

LATCH-UP PHENOMENA

The early ageing and destruction of IC’s is often due to latch-up phenomenon which is mainly induced by

dV/dt. Thanks to its structure, the USBUFxxW6 provides a high immunity to latch-up phenomenon by

smoothing very fast edges.

CROSSTALK BEHAVIOR

Fig. A8: Crosstalk phenomenon

R_G1

Line 1

V_G1

R_L1

α₁V_G1+ β₁₂V_G2

R_G2

Line 2

V_G2

R_L2

α₂V_G2+ β₂₁V_G1

DRIVERS

RECEIVERS

The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor ( β₁₂or β₂₁) in-

creases when the gap across lines decreases, particularly in silicon dice. In the example above the ex-

pected signal on load R_L2is α₂V_G2, in fact the real voltage at this point has got an extra value β₂₁V_G1. This

part of the V_G1signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This

phenomenon has to be taken into account when the drivers impose fast digital data or high frequency ana-

log signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal

or high load impedance (few kΩ).

6/9

USBUFxxW6

Fig. A9: Analog crosstalk measurements

Fig. A10: Typical analog crosstalk results

Analog crosstalk (dB)

-20

-40

TEST BOARD

50Ω

UUx

50Ω

-60

-80

-100

100

1,000

Frequency (MHz)

Figure A9 gives the measurement circuit for the analog crosstalk application. In figure A10, the curve

shows the effect of the D+ cell on the D- cell. In usual frequency range of analog signals (up to 100MHz) the

effect on disturbed line is less than -37dB.

Fig. A11: Digital crosstalk measurements configuration

+5V

74HC04

3.3 V

D+

3.3 V

V_G1

Square

Pulse

Gnd

+5V

D-

Generator

₂₁V_G1

Figure A11 shows the measurement circuit used to quantify the crosstalk effect in a classical digital appli-

cation.

Fig. A12: Digital crosstalk results

Figure A12 shows, with a signal from 0 to 5V and

rise time of few ns, the impact on the disturbed line

is less than 250mV peak to peak. No data distur-

bance was noted on the other line.The measure-

ments performed with falling edges gives an

impact within the same range.

VG1

β21VG1

7/9

USBUFxxW6

TRANSITION TIMES

This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the

signal edges are maintained within the 4ns-20ns stipulated USB specification limits. To verify this point, we

have measured the rise time of VD+ voltage (please refer to Fig. A13) with and without the USBUFxxW6

device.

Fig. A13: Typical rise and fall times: measure-

ments configuration

Fig. A14: Typical rise times with and without pro-

tection device

without

+5V

74HC04

D+

+5V

USBUF

-xxW6

VD+

+5V

Square

Pulse

D-

Generator

with

Figure A13 shows the circuit used to perform measurements of the transition times. In Figure A14, we see

the results of such measurements:

trise = 3.8ns

trise = 7.8ns

driver alone

with protection device

The adding of the protection device causes the rise time increase of roughly 4ns.

Note: Rise time has been measured between 10% and 90% of the signal (resp. 90% and 10%)

8/9

USBUFxxW6

PACKAGE MECHANICAL DATA.

SOT323-6L

DIMENSIONS

Millimeters Inches

Min.

REF.

Min.

0.8

Max.

0.043

0.004

0.039

0.012

0.007

0.086

0.053

1.1

0.1

0.031

0.8

0.15

0.1

1.8

1.15

0.031

0.006

0.004

0.071

0.045

0.3

0.18

2.2

1.35

0.65 Typ.

0.025 Typ.

1.8

0.1

2.4

0.4

0.071

0.004

0.094

0.016

MECHANICAL SPECIFICATIONS

RECOMMENDED FOOTPRINT (mm)

0.3mm

Lead plating

Tin-lead

Lead plating thickness

5µm min

25µm max

1mm

Lead material

Sn / Pb

(70% to 90%Sn)

2.9mm

Lead coplanarity

Body material

Flammability

10µm max

Molded epoxy

UL94V-0

1mm

0.35mm

MARKING

Ordering code

USBUF01W6

USBUF02W6

Marking

UU1

Package

SOT323-6L

Weight

5.4 mg

Base qty

Delivery mode

Tape & reel

3000

UU2

Tape & reel

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of

use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by

implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied.

STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-

proval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - Finland - France - Germany

Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore

Spain - Sweden - Switzerland - United Kingdom - United States.

http://www.st.com

9/9

USBUF01W6相关文章

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USBUF02W6产品参数

型号:	USBUF02W6
Brand Name：	STMicroelectronics
生命周期：	Active
IHS 制造商：	STMICROELECTRONICS
零件包装代码：	SC-70
包装说明：	TSSOP, TSSOP6,.08
针数：	6
制造商包装代码：	SOT323
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	43 weeks 2 days
风险等级：	0.68
差分输出：	YES
接口集成电路类型：	OTHER TERMINATOR
JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e3
长度：	2 mm
湿度敏感等级：	1
功能数量：	1
信号线数量：	2
端子数量：	6
最高工作温度：	70 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP6,.08
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Bus Terminators
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	OTHER
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	1.25 mm
Base Number Matches：	1

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