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芯片VN5050JTR-E的概述 VN5050JTR-E是一款由意法半导体（STMicroelectronics）制造的高压功率MOSFET驱动器，特别设计用于汽车和工业应用中，支持直流电机驱动、灯光控制、和其他负载的驱动。这种芯片能够提供高电流输出，具有内部保护功能，确保系统在极端工作条件下的稳定性。随着电气设备对高效能和安全性的需求不断增加，VN5050JTR-E以其卓越的性能，成为众多设计工程师的首选。芯片VN5050JTR-E的详细参数 VN5050JTR-E具有一系列重要的技术参数，使其适用于多种应用环境。其主要参数如下： - 工作电压: 最大50V，适合较高电压环境下的应用。 - 输出电流: 最大可承受30A的连续电流，并具有高达70A的瞬时电流能力。 - 功耗: 低功耗设计，确保在长时间工作中保持高效能。 - 温度范围: 工作温度范围为-40°C至+150°C，适合苛刻...

产品型号VN5050JTR-E的Datasheet PDF文件预览

VN5050J-E

Single channel high side driver for automotive applications

Features

General

Max supply voltage

V_CC

41V

PowerSSO-12 (Slug down)

■ Load current limitation

■ Self limiting of fast thermal transients

■ Protection against loss of ground and loss of

Operating voltage range

Max On-State resistance

Current limitation (typ)

Off state supply current (TYP)

V_CC4.5 to 36V

R_ON

I_LIMH

I_S

50 mΩ

19A

2 µA

■ Thermal shut down

Application

■ Reverse battery protection (see Figure 28)

■ Electrostatic discharge protection

■ All types of resistive, inductive and capacitive

loads

Main

Description

■ Inrush current active management by power

limitation

■ Very low stand-by current

■ 3.0V CMOS compatible input

The VN5050J-E is a monolithic device made

using STMicroelectronics VIPower technology. It

is intended for driving resistive or inductive loads

with one side connected to ground. Active V pin

■ Optimized electromagnetic emission

■ Very low electromagnetic susceptibility

■ In compliance with the 2002/95/ec european

voltage clamp protects the device against low

energy spikes (see ISO7637 transient

compatibility table). The device detects open load

condition both in on and off state, when STAT_DIS

directive

is left open or driven low. Output shorted to V is

detected in the off state.

Diagnostic Functions

■ Open drain status output

When STAT_DIS is driven high, the STATUS pin

is in a high impedance condition.

■ On state open load detection

■ Off state open load detection

■ Thermal shutdown indication

Output current limitation protects the device in

overload condition. In case of long duration

overload, the device limits the dissipated power to

safe level up to thermal shut-down intervention.

Protections

■ Undervoltage shut-down

■ Overvoltage clamp

■ Output stuck to Vcc detection

Thermal shut-down with automatic restart allows

the device to recover normal operation as soon as

fault condition disappears..

Order codes

Package

Part number (Tube)

VN5050J-E

Part number (Tape & Reel)

PowerSSO-12 (slug down)

VN5050JTR-E

March 2006

Rev 1

1/23

www.st.com

Contents

VN5050J-E

Contents

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1

2.2

2.3

2.4

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

GND Protection Network Against Reverse Battery . . . . . . . . . . . . . . . . . 15

3.1.1

3.1.2

Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2

3.3

3.4

Load Dump Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

µC I/Os PROTECTION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package and PCB Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

PowerSSO-12 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

5.2

Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/23

VN5050J-E

Block diagram and pin description

Figure 1. Block Diagram

UNDERVOLTAGE

PwCLAMP

CLAMP

DRIVER

GND

INPUT

OUTPUT

LIM

DSLIM

LOGIC

STATUS

OPENLOAD ON

STAT_DIS

OPENLOAD OFF

OVERTEMP.

Pwr

LIM

Table 1.

Name

V_CC

Pin Function

Function

Battery connection

Power output

OUTPUT

GND

Ground connection. Must be reverse battery protected by an external

diode/resistor network

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output

switch state

INPUT

STATUS

Open drain digital diagnostic pin

STAT_DIS

Active high CMOS compatible pin, to disable the STATUS pin

Figure 2. Configuration Diagram (Top View) & Suggested Connections For Unused

and n.c. Pins

TAB = V_cc

OUTPUT

GND

INPUT

STAT_DIS

STATUS

Connection / Pin

Status

N.C.

Output

Input

STAT_DIS

Floating

To Ground

N.R.

10KΩ resistor 10KΩ resistor

N.R. = Not recommended

3/23

Electrical specifications

VN5050J-E

Electrical specifications

Figure 3. Current and Voltage Conventions

V_CC

OUT

STAT_DIS

INPUT

OUTPUT

STATUS

OUT

STAT

GND

= V

- V during reverse battery condition

OUT CC

2.1

Absolute Maximum Ratings

Table 2.

Symbol

Absolute Maximum Ratings

Parameter

Value

Unit

V_CC

-V_CC

-I_GND

I_OUT

-I_OUT

I_IN

DC supply voltage

0.3

200

Reverse DC supply voltage

DC reverse ground pin current

DC output current

Internally limited

Reverse DC output current

DC input current

+10 / -1

I_STAT

DC status current

I_{STAT_DIS}DC status disable current

Maximum switching energy

E_MAX

(L=1.5mH; R_L=0Ω; V_bat=13.5V; T_jstart=150°C; I_OUT

I_limL(Typ.) )

Electrostatic Discharge (Human Body Model: R=1.5KΩ;

C=100pF)

4000

5000

– INPUT

V_ESD

– STATUS

– STAT_DIS

– OUTPUT

– V_CC

V_ESD

T_j

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

750

-40 to 150

-55 to 150

°C

T_stg

4/23

VN5050J-E

Electrical specifications

2.2

Thermal Data

Table 3.

Symbol

Thermal Data

Parameter

Max Value

Unit

°C/W

R_thj-caseThermal resistance junction-case

R_thj-ambThermal resistance junction-ambient

2.8

See Figure 31

2.3

Electrical Characteristics

8V<V <36V; -40°C<T <150°C, unless otherwise specified.

Table 4.

Symbol

Power section

Parameter

Test Conditions

Min.

Typ. Max. Unit

V_CC

Operating supply voltage

Undervoltage shutdown

4.5

V_USD

3.5

4.5

Undervoltage Shut-down

hysteresis

V_USDhyst

0.5

_OUT=1A; T_j=25°C

100

mΩ

R_ON

V_clamp

I_S

On state resistance

Clamp Voltage

I_OUT=1A; T_j=150°C

I_OUT=1A; V_CC=5V; T_j=25°C

I_S=20mA

Off State; V_CC=13V; V_IN=V_OUT=0

T_j=25°C;

Supply current

2⁽¹⁾

1.9

5⁽¹⁾

3.5

µA

On State; V_CC=13V; V_IN=5V; I_OUT=0A

V_IN=V_OUT=0V; V_CC=13V; T_j=25°C

V_IN=V_OUT=0V; V_CC=13V; T_j=125°C

0.01

I_L(off1)

Off state output current

µA

I_L(off2)

V_F

V_IN=0V; V_OUT=4V

-75

Output - V_CCdiode voltage

-I_OUT=2A; T_j=150°C

0.7

(1) PowerMOS leakage included.

Table 5.

Symbol

t_d(on)

t_d(off)

Switching (V =13V)

Parameter

Test Conditions

Min.

Typ. Max. Unit

Turn-on delay time

Turn-off delay time

R_L=6.5Ω (see Figure 6)

R_L=6.5Ω

µs

dV_OUT/dt_(on)Turn-on voltage slope

dV_OUT/dt_(off)Turn-off voltage slope

see Figure 21

see Figure 22

V/µs

R_L=6.5Ω

Switching energy losses

during t_won

W_ON

R_L=6.5Ω (see Figure 6)

0.2

Switching energy losses

during t_woff

W_OFF

5/23

Electrical specifications

VN5050J-E

Table 6.

Symbol

V_STAT

Status Pin (V =0)

Parameter

Test Conditions

Min.

Typ. Max. Unit

Status Low Output Voltage

Status Leakage Current

I_STAT= 1.6 mA, V_SD=0V

0.5

Normal Operation or V_SD=5V,

_STAT= 5V

I_LSTAT

C_STAT

µA

Status Pin Input

Capacitance

Normal Operation or V_SD=5V,

V_STAT= 5V

100

_STAT= 1mA

5.5

V_SCL

Status Clamp Voltage

I_STAT= - 1mA

-0.7

(1)

Table 7.

Symbol

Protections

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

V_CC=13V

13.5

26.5

I_limH

DC Short circuit current

5V<V_CC<36V

Short circuit current during

thermal cycling

I_limL

V_CC=13V T_R<T_j<T_TSD

T_TSD

T_R

Shutdown temperature

Reset temperature

150

175

200

°C

+ 1 T_RS+ 5

T_RS

Thermal reset of STATUS

135

T_HYST

Thermal hysteresis (T

-T )

TSD

Status Delay in Overload

Conditions

t_SDL

V_DEMAG

V_ON

T_j>T_TSD

µs

I_OUT=2A; V_IN=0; L=6mH

Turn-off output voltage

clamp

V_CC-41 V_CC-46 V_CC-52

Output voltage drop

limitation

I_OUT=0.3A; T_j= -40°C...+150°C

(see Figure 5)

(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals

must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must

limit the duration and number of activation cycles

Table 8.

Symbol

Openload Detection

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Openload ON State

Detection Threshold

See

Figure 19

I_OL

V_IN= 5V, 8V<V_CC<18V

Openload ON State

Detection Delay

I_OUT= 0A, V_CC=13V

(see fig. Figure 4)

t_DOL(on)

200

µs

Delay between INPUT falling

edge and STATUS rising

edge in Openload condition

t_POL

I_OUT= 0A (see fig. Figure 4)

200

500

1000

Openload OFF State Voltage

Detection Threshold

See

Figure 20

V_OL

V_IN= 0V, 8V<V_CC<16V

Output Short Circuit to V_cc

Detection Delay at Turn Off

t_DSTKON

(see fig. Figure 4)

180

t_POL

µs

6/23

VN5050J-E

Electrical specifications

Table 9.

Symbol

Logic input

Parameter

Test Conditions

Min.

Typ. Max. Unit

V_IL

I_IL

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

0.9

µA

V_IN=0.9V

V_IN=2.1V

V_IH

2.1

I_IH

µA

V_I(hyst)

0.25

5.5

I_IN=1mA

I_IN=-1mA

V_ICL

Input clamp voltage

-0.7

V_CSDL

I_CSDL

V_CSDH

I_CSDH

CS_DIS low level voltage

Low level CS_DIS current

CS_DIS high level voltage

High level CS_DIS current

0.9

µA

V_CSD=0.9V

V_CSD=2.1V

2.1

µA

V_CSD(hyst)CS_DIS hysteresis voltage

V_CSCLCS_DIS clamp voltage

0.25

5.5

_CSD=1mA

I_CSD=-1mA

-0.7

Figure 4. Status Timings

OPEN LOAD STATUS TIMING (with external pull-up)

< I

OPEN LOAD STATUS TIMING (without external pull-up)

< I

OUT

> V

< V

OUT

STAT

DOL(on)

POL

OVER TEMP STATUS TIMING

T_j> T_TSD

OUTPUT STUCK TO Vcc

I_OUT> I_OL

V_IN

V_OUT> V_OL

V_STAT

t_DOL(on)

t_SDL

t_DSTKON

t_SDL

7/23

Electrical specifications

Figure 5. Output Voltage Drop Limitation

VN5050J-E

V_cc-V_out

T =150 C

T =25 C

T =-40 C

V_on

I_out

V_on/R_on(T)

Table 10. Truth table

CONDITIONS

INPUTn

OUTPUTn

STATUSn (V_SD=0V)⁽¹⁾⁾

Normal Operation

Current Limitation

Overtemperature

Undervoltage

L⁽²⁾

Output Voltage > V_OL

Output Current < I_OL

H⁽³⁾

(1) If the V_SDis high, the STATUS pin is in a high impedance.

(2) The STATUS pin is low with a delay equal to t_DSTKONafter INPUT falling edge.

(3) The STATUS pin becomes high with a delay equal to t_POLafter INPUT falling edge.

Figure 6. Switching characteristics

OUT

Won

Woff

90%

80%

/dt

OUT (off)

OUT (on)

10%

INPUT

d(on)

d(off)

8/23

VN5050J-E

Electrical specifications

Table 11. Electrical Transient Requirements

ISO 7637-2:

2004(E)

TEST LEVELS

Number of

pulses or

test times

Burst cycle/pulse repetition

time

Delays and

Impedance

III

Test Pulse

-75V

+37V

-100V

+75V

-6V

-100V

+50V

-150V

+100V

-7V

5000 pulses

1 pulse

0.5 s

0.2 s

90 ms

5 s

100 ms

2 ms, 10 Ω

50 µs, 2 Ω

0.1 µs, 50 Ω

100 ms, 0.01 Ω

400 ms, 2 Ω

5b⁽¹⁾

+40V

ISO 7637-2:

2004(E)

TEST LEVEL RESULTS

III

Test Pulse

5⁽¹⁾

CLASS

CONTENTS

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance

and cannot be returned to proper operation without replacing the device.

(1) For load dump exceeding the above value a centralized suppressor must be adopted.

9/23

Electrical specifications

Figure 7. Waveforms

VN5050J-E

NORMAL OPERATION

UNDERVOLTAGE

INPUT

STAT_DIS

LOAD CURRENT

STATUS

USDhyst

V_CC

USD

INPUT

STAT_DIS

LOAD CURRENT

STATUS

undefined

OPEN LOAD with external pull-up

INPUT

STAT_DIS

V_OUT>V_OL

LOAD VOLTAGE

STATUS

V_OL

OPEN LOAD without external pull-up

INPUT

STAT_DIS

LOAD VOLTAGE

LOAD CURRENT

STATUS

I_OUT<I_OL

POL

RESISTIVE SHORT TO Vcc, NORMAL LOAD

INPUT

STAT_DIS

I_OUT>I_OL

V_OUT>V_OL

LOAD VOLTAGE

STATUS

V_OL

DSTKON

OVERLOAD OPERATION

TSD

T_j

INPUT

STAT_DIS

LIMH

LIML

LOAD CURRENT

STATUS

thermal cycling

SHORTED LOAD

current

limitation

power

limitation

NORMAL LOAD

10/23

VN5050J-E

Electrical specifications

2.4

Electrical characteristics curves

Figure 8. Off State Output Current

Figure 9. Input Clamp Voltage

Iloff1 (uA)

0.25

Vicl (V)

7.75

7.5

Iin=1mA

0.2

Off state

Vcc=13V

Vin=Vout=0V

7.25

0.15

0.1

0.05

6.75

6.5

6.25

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

Figure 10. High Level Input Current

Figure 11. Input High Level

Iih (uA)

Vih (V)

4.5

3.5

Vin=2.1V

3.5

2.5

1.5

0.5

-50

-25

100

125

-50

-25

100

125

Tc (°C)

Figure 12. Input Low Level

Figure 13. Input Hysteresis Voltage

Vil (V)

Vihyst (V)

3.5

1.75

1.5

1.25

2.5

1.5

0.75

0.5

0.25

0.5

-50

-25

100

125

-50

-25

100

125

Tc (°C)

11/23

Electrical specifications

VN5050J-E

Figure 14. Status Low Output Voltage

Figure 15. Status Leakage Current

Ilstat (uA)

0.055

Vstat (V)

0.9

0.8

0.05

Istat=1.6mA

0.7

Vstat=5V

0.045

0.6

0.5

0.4

0.3

0.2

0.1

0.04

0.035

0.03

0.025

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

Figure 16. Status Clamp Voltage

Figure 17. On State Resistance Vs T

case

Vscl (V)

Ron (mOhm)

100

8.5

Istat=1mA

Iout=2A

Vcc=13V

7.5

6.5

5.5

4.5

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

Figure 18. On State Resistance Vs V

Figure 19. Openload On State Detection

Threshold

Ron (mOhm)

100

Iol (mA)

100

Vin=5V

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

-50

-25

100

125

150

175

Vcc

Tc (°C)

12/23

VN5050J-E

Electrical specifications

Figure 20. Openload Off State Voltage

Detection Threshold

Figure 21. Turn-on Voltage Slope

Vol (V)

dVout/dt(on) (V/ms)

1000

900

4.5

Vcc=13V

Ri=6.5Ohm

Vin=0V

800

700

600

500

400

300

200

100

3.5

2.5

1.5

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

Figure 22. Turn-off Voltage Slope

Figure 23. I

Vs T

LIM

case

Ilimh (A)

dVout/dt(off) (V/ms)

1000

900

22.5

Vcc=13V

Ri=6.5Ohm

Vcc=13V

800

700

17.5

600

500

400

300

200

100

12.5

7.5

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

Figure 24. Undervoltage Shutdown

Figure 25. STAT_DIS Clamp Voltage

Vusd (V)

Vsdcl (V)

Isd=1mA

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

13/23

Electrical specifications

VN5050J-E

Figure 26. High Level STAT_DIS Voltage

Figure 27. Low Level STAT_DIS Voltage

Vsdh (V)

Vsdl (V)

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C)

14/23

VN5050J-E

Application Information

Figure 28. Application schematic

+5V

prot

STAT_DIS

INPUT

prot

µC

OUTPUT

STATUS

prot

GND

3.1

GND Protection Network Against Reverse Battery

3.1.1

Solution 1:

Resistor in the ground line (R

only). This can be used with any type of load.

GND

The following is an indication on how to dimension the R

resistor.

GND

≤ 600mV / (I

S(on)max

GND

≥ (−V ) / (-I

)

GND

where -I

is the DC reverse ground pin current and can be found in the absolute

GND

maximum rating section of the device datasheet.

Power Dissipation in R

(when V <0: during reverse battery situations) is:

GND

P = (-V ) /R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of

this resistor should be calculated with formula (1) where I

maximum on-state currents of the different devices.

becomes the sum of the

S(on)max

Please note that if the microprocessor ground is not shared by the device ground then the

will produce a shift (I * R ) in the input thresholds and the status output

GND

S(on)max

GND

values. This shift will vary depending on how many devices are ON in the case of several

high side drivers sharing the same R

GND

15/23

Application Information

VN5050J-E

If the calculated power dissipation leads to a large resistor or several devices have to share

the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2

Solution 2:

A diode (D

) in the ground line.

GND

A resistor (R

=1kΩ) should be inserted in parallel to D

if the device drives an

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this

case, the presence of the ground network will produce a shift (≈600mV) in the input

threshold and in the status output values if the microprocessor ground is not common to the

device ground. This shift will not vary if more than one HSD shares the same diode/resistor

network.

3.2

3.3

Load Dump Protection

D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the

max DC rating. The same applies if the device is subject to transients on the V line

that are greater than the ones shown in the ISO 7637-2: 2004 (E) table.

µC I/Os PROTECTION:

If a ground protection network is used and negative transient are present on the V line,

the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to

prot

prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the

current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC

I/Os.

-V

≤ R

≤ (V

-V -V

) / I

CCpeak latchup

prot

OHµC IH GND IHmax

Calculation example:

For V = - 100V and I

≥ 20mA; V ≥ 4.5V

OHµC

CCpeak

latchup

5kΩ ≤ R

≤ 180kΩ.

prot

Recommended R

values is 10kΩ.

prot

3.4

Open load detection in off state

Off state open load detection requires an external pull-up resistor (RPU) connected between

OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the

microprocessor.

The external resistor has to be selected according to the following requirements:

1. no false open load indication when load is connected: in this case we have to avoid

to be higher than V

; this results in the following condition

OUT

Olmin

=(V /(R +R ))R <V .

Olmin

2. no misdetection when load is disconnected: in this case the V

has to be higher than

OUT

; this results in the following condition R <(V –V

)/I

OLmax

PU OLmax L(off2)

16/23

VN5050J-E

Application Information

may significantly increase if V is pulled high (up to several mA), the pull-

Because I

s(OFF)

out

up resistor R should be connected to a supply that is switched OFF when the module is in

standby.

The values of V

section.

, V

and I

are available in the Electrical Characteristics

OLmin OLmax

L(off2)

Figure 29. Open Load detection in off state

V batt.

V^CC

RPU

DRIVER

IL(off2)

INPUT

LOGIC

OUT

STATUS

VOL

GROUND

17/23

Package and PCB Thermal Data

VN5050J-E

Package and PCB Thermal Data

4.1

PowerSSO-12 Thermal Data

Figure 30. PowerSSO-12 PC Board

Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,

PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm ).

Figure 31. R

Vs. PCB copper area in open box free air condition

thj-amb

RTHj_amb(°C/W)

PCB Cu heatsink area (cm^2)

Figure 32. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse

ZTH (°C/W)

1000

Footprint

100

2 cm

8 cm

0.1

0.0001 0.001

0.01

0.1

100

1000

Time (s)

Pulse Calculation Formula

= R ⋅ δ + Z (1 – δ)

THδ

THtp

where δ = t /T

18/23

VN5050J-E

Package and PCB Thermal Data

Figure 33. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12

Thermal Parameter

Area/island (cm²)

Footprint

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

0.7

2.8

0.001

0.0025

0.05

0.2

0.27

0.1

0.8

0.1

19/23

Package information

VN5050J-E

Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.1

Package Mechanical

Figure 34. PowerSSO-12™ Package Dimensions

0.25 mm

GAUGE PLANE

h x 45˚

SEATING

PLANE

ddd

BOTTOM

VIEW

Table 12. PowerSSO-12™ Mechanical Data

millimeters

Typ

Symbol

Min

Max

1.250

0.000

1.100

0.230

0.190

4.800

3.800

1.620

0.100

1.650

0.410

0.250

5.000

4.000

0.800

5.800

0.250

0.400

0°

6.200

0.500

1.270

8°

ddd

1.900

3.600

2.500

4.200

0.100

20/23

VN5050J-E

Package information

5.2

Packing information

Figure 35. PowerSSO-12 Tube Shipment (No Suffix)

Base Q.ty

100

2000

532

Bulk Q.ty

Tube length ( 0.5)

1.85

6.75

0.6

C ( 0.1)

All dimensions are in mm.

Figure 36. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)

REEL DIMENSIONS

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C ( 0.2)

2500

330

1.5

20.2

12.4

G (+ 2 / -0)

N (min)

T (max)

18.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Position

P0 ( 0.1)

D ( 0.05)

D1 (min)

F ( 0.1)

K (max)

P1 ( 0.1)

1.5

5.5

4.5

Compartment Depth

Hole Spacing

All dimensions are in mm.

End

Start

Top

No components

500mm min

Components

No components

500mm min

cover

tape

Empty components pockets

saled with cover tape.

User direction of feed

21/23

Revision history

VN5050J-E

Revision history

Table 13. Document revision history

Date

Revision

Changes

30-Mar-2006

Initial release.

22/23

VN5050J-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,

AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS,

NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR

SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

23/23

VN5050JTR-E相关文章

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VN5050JTR-E产品参数

型号:	VN5050JTR-E
Brand Name：	STMicroelectronics
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	STMICROELECTRONICS
零件包装代码：	SSOP
包装说明：	HLSSOP, SOP12,.25,32
针数：	12
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	18 weeks
风险等级：	1.64
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	527254
Samacsys Pin Count：	13
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	VN5050JTR-E
Samacsys Released Date：	2019-01-10 07:58:44
Is Samacsys：	N
内置保护：	TRANSIENT; OVER CURRENT; OVER VOLTAGE; THERMAL; UNDER VOLTAGE
驱动器位数：	1
接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：	R-PDSO-G12
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	12
输出电流流向：	SINK
封装主体材料：	PLASTIC/EPOXY
封装代码：	HLSSOP
封装等效代码：	SOP12,.25,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	225
电源：	8/36 V
认证状态：	Not Qualified
座面最大高度：	1.62 mm
子类别：	Peripheral Drivers
最大供电电压：	36 V
最小供电电压：	4.5 V
标称供电电压：	13 V
表面贴装：	YES
技术：	CMOS
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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