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W6810

SINGLE-CHANNEL VOICEBAND CODEC

Preliminary Data Sheet

Publication Release Date: October 10, 2002

Revision A9

- 1 -

W6810

1. GENERAL DESCRIPTION

The W6810 is a general-purpose single channel PCM CODEC with pin-selectable µ-Law or A-Law

companding. The device is compliant with the ITU G.712 specification. It operates off of a single +5V

power supply and is available in 20-pin PDIP, SOG, SSOP, and TSSOP package options. Functions

performed include digitization and reconstruction of voice signals, and band limiting and smoothing

filters required for PCM systems. The filters are compliant with ITU G.712 specification. W6810

performance is specified over the industrial temperature range of –40°C to +85°C.

The W6810 includes an on-chip precision voltage reference and an additional power amplifier,

capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is

fully differential, reducing noise and improving the power supply rejection ratio. The data transfer

protocol supports both long-frame and short-frame synchronous communications for PCM

applications, and IDL and GCI communications for ISDN applications. W6810 accepts seven master

clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically determines the

division ratio for the required internal clock.

For fast evaluation and prototyping purposes, the W6810DK development kit is available.

2. FEATURES

APPLICATIONS

•

Digital Telephone Systems

•

Single +5V power supply

•

Central Office Equipment (Gateways,

Switches, Routers)

•

Typical power dissipation of 25 mW,

power-down mode of 0.5 µW

•

PBX Systems (Gateways, Switches)

PABX/SOHO Systems

Local Loop card

SOHO Routers

VoIP Terminals

Enterprise Phones

ISDN Terminals

Analog line cards

•

Fully-differential analog circuit design

On-chip precision reference of 1.575 V for

a 0 dBm TLP at 600 Ω

•

Push-pull power amplifiers with external

gain adjustment with 300 Ω load capability

Seven master clock rates of 256 kHz to

4.096 MHz

Pin-selectable

µ-Law

and

A-Law

companding (compliant with ITU G.711)

CODEC A/D and D/A filtering compliant

with ITU G.712

Industrial temperature range (–40°C to

+85°C)

Four packages: 20-pin PDIP, SOG, SSOP,

and TSSOP

Digital Voice Recorders

- 2 -

W6810

3. BLOCK DIAGRAM

BCLKR

FSR

Re

cei

ve

Int

erf

ace

PC

M

PAO+

PAO-

PAI

PCMR

G.712 CODEC

RO-

AO

Tra

ns

BCLKT

Int

erf

ace

G.711 /A-Law

µ

PC

M

AI+

AI-

FST

mit

PCMT

/A-Law

µ

V_REF

512 kHz

256 kHz

V_AG

MCLK

Voltage reference

Pre-Ssccaalleerr

8 kHz

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

& 4096 kHz

Power Conditioning

Publication Release Date: October 10, 2002

Revision A9

- 3 -

W6810

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM .............................................................................................................................. 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION............................................................................................................ 8

7.1. Transmit Path............................................................................................................................. 8

7.2. Receive Path.............................................................................................................................. 9

7.3. Power Management................................................................................................................. 10

7.3.1. Analog and Digital Supply.............................................................................................. 10

7.3.2. Analog Ground Reference Bypass................................................................................. 10

7.3.3. Analog Ground Reference Voltage Output .................................................................... 10

7.4. PCM Interface.......................................................................................................................... 10

7.4.1. Long Frame Sync........................................................................................................... 11

7.4.2. Short Frame Sync .......................................................................................................... 11

7.4.3. GCI Interface.................................................................................................................. 11

7.4.4. IDL Interface................................................................................................................... 12

7.4.5. System Timing................................................................................................................ 12

8. TIMING DIAGRAMS.......................................................................................................................... 13

9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20

9.1. Absolute Maximum Ratings..................................................................................................... 20

9.2. Operating Conditions............................................................................................................... 20

10. ELECTRICAL CHARACTERISTICS............................................................................................... 21

10.1. General Parameters .............................................................................................................. 21

10.2. Analog Signal Level and Gain Parameters............................................................................ 22

10.3. Analog Distortion and Noise Parameters .............................................................................. 23

10.4. Analog Input and Output Amplifier Parameters..................................................................... 24

10.5. Digital I/O ............................................................................................................................... 26

10.5.1. µ-Law Encode Decode Characteristics........................................................................ 26

10.5.2. A-Law Encode Decode Characteristics ....................................................................... 27

10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 28

10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 28

11. TYPICAL APPLICATION CIRCUIT................................................................................................. 29

12. PACKAGE SPECIFICATION .......................................................................................................... 31

- 4 -

W6810

12.1. 20L TSSOP – 4.4X6.5mm ..................................................................................................... 31

12.2. 20L SOP – 300mil.................................................................................................................. 32

12.3. 20L SSOP – 209mil ............................................................................................................... 33

12.4. 20L PDIP................................................................................................................................ 34

13. ORDERING INFORMATION........................................................................................................... 35

14. VERSION HISTORY ....................................................................................................................... 36

Publication Release Date: October 10, 2002

- 5 -

Revision A9

W6810

5. PIN CONFIGURATION

V_AG

AI+

AI-

V_REF

RO-

1

2

20

19

18

17

16

15

14

13

12

11

3

PAI

AO

PAO-

PAO+

V_DD

4

SINGLE

CHANNEL

CODEC

/A-Law

5

µ

V_SS

6

FST

FSR

7

PCMT

BCLKT

MCLK

PCMR

BCLKR

PUI

8

9

10

PDIP/SOG/SSOP/TSSOP

- 6 -

W6810

6. PIN DESCRIPTION

Pin Functionality

Name

No.

V_REF

1

2

This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to V_SS

through a 0.1 µF ceramic decoupling capacitor. No external loads should be tied to this pin.

RO-

Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 1.575

volt peak referenced to the analog ground level.

PAI

PAO-

3

4

This pin is the inverting input to the power amplifier. Its DC level is at the V_AGvoltage.

Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced

to the V_AGvoltage level.

PAO+

5

Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak

referenced to the V_AGvoltage level.

V_DD

6

7

Power supply. This pin should be decoupled to V_SSwith a 0.1µF ceramic capacitor.

FSR

8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or

channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit

and receive are synchronous operations.

PCMR

BCLKR

8

9

PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.

PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is

selected when this pin is tied to V_SS. The IDL mode is selected when this pin is tied to V_DD.

This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.

PUI

10

11

Power up input signal. When this pin is tied to V_DD, the part is powered up. When tied to V_SS,

the part is powered down.

System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544

kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have

the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the

case of 256 and 512 kHz frequency.

MCLK

BCLKT

PCMT

FST

12

13

14

15

16

PCM transmit bit clock input pin.

PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.

8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.

This is the supply ground. This pin should be connected to 0V.

V_SS

µ/A-Law

Compander mode select pin. µ-Law companding is selected when this pin is tied to V_DD. A-Law

companding is selected when this pin is tied to V_SS.

AO

AI-

AI+

V_AG

17

18

19

20

Analog output of the first gain stage in the transmit path.

Inverting input of the first gain stage in the transmit path.

Non-inverting input of the first gain stage in the transmit path.

Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal

processing. This pin should be decoupled to V_SSwith a 0.01µF capacitor. This pin becomes

high impedance when the chip is powered down.

Publication Release Date: October 10, 2002

- 7 -

Revision A9

W6810

7. FUNCTIONAL DESCRIPTION

W6810 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies

with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete µ-

Law and A-Law compander. The µ-Law and A-Law companders are designed to comply with the

specifications of the ITU-T G.711 recommendation.

The block diagram in section 3 shows the main components of the W6810. The chip consists of a

PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.

The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample

rate with the external frame sync frequency. The power conditioning block provides the internal

power supply for the digital and the analog section, while the voltage reference block provides a

precision analog ground voltage for the analog signal processing. The main CODEC block diagram

is shown in section 3.

+

-

+

A

V_AG

PAO+

G

-

PAO

PAI

Receive Path

8

D/A

-

RO

Converter

f

C

= 3400Hz

w

H

Smoot

Smoothing

/

A--

µ

Filter

n

Filter

n

Cont

Control

1

2

ol

Transmit Path

AO

AI+

8

A/D

+

Converter

f

C

f

^C

= 3400Hz

-Aliasing

-

= 200Hz

_C

= 200

-

AI

=

µ

-

/A

H

i

H

gh Pass

A

n

H

t

High

Ant Aliasi

An

t

-

Aliasing

Filter

/

A

-

µ

Control

Filter

n

Filter

Cont

Pas

i

Figure 7.1 The W6810 Signal Path

7.1. Transmit Path

The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain

setting (see application examples in section 11). The device has an input operational amplifier whose

output is the input to the encoder section. If the input amplifier is not required for operation it can be

powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or

the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The

input amplifier can be powered down by connecting the AI+ pin to V_DDor V_SS. The AO pin is selected

as an input when AI+ is tied to V_DDand the AI- pin is selected as an input when AI+ is tied to V_SS(see

Table 7.1).

- 8 -

W6810

AI+

Input Amplifier

Input

V_DD

1.2 to V_DD-1.2

V_SS

Powered Down

Powered Up

Powered Down

AO

AI+, AI-

AI-

Table 7.1 Input Amplifier Modes of operation

When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the

analog ground voltage V_AG.

The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched

capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of

input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is

filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the

recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is

digitized. The signal is converted into a compressed 8-bit digital representation with either µ-Law or A-

Law format. The µ-Law or A-Law format is pin-selectable through the µ/A-Law pin. The compression

format can be selected according to Table 7.2.

Format

µ/A-Law Pin

V_SS

V_DD

A-Law

µ-Law

Table 7.2. Pin-selectable Compression Format

The digital 8-bit µ-Law or A-Law samples are fed to the PCM interface for serial transmission at the

sample rate supplied by the external frame sync FST.

7.2. Receive Path

The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and

converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed

through the pin-selectable µ-Law or A-Law expander and converted to analog samples. The mode of

expansion is selected by the µ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a

low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.

A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is

buffered to provide the receive output signal RO-. The RO- output can be externally connected to the

PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By

using external resistors (see section 11 for examples), various gain settings of this output amplifier

can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting

PAI to V_DD.

Publication Release Date: October 10, 2002

- 9 -

Revision A9

W6810

7.3. POWER MANAGEMENT

7.3.1. Analog and Digital Supply

The power supply for the analog and digital parts of the W6810 must be 5V +/- 10%. This supply

voltage is connected to the V_DDpin. The V_DDpin needs to be decoupled to ground through a 0.1 µF

ceramic capacitor.

7.3.2. Analog Ground Reference Bypass

The system has an internal precision voltage reference which generates the 2.5V mid-supply analog

ground voltage. This voltage needs to be decoupled to V_SSat the V_REFpin through a 0.1 µF ceramic

capacitor.

7.3.3. Analog Ground Reference Voltage Outpt

The analog ground reference voltage is available for external reference at the V_AGpin. This voltage

needs to be decoupled to V_SSthrough a 0.01 µF ceramic capacitor. The analog ground reference

voltage is generated from the voltage on the V_REFpin and is also used for the internal signal

processing.

7.4. PCM INTERFACE

The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received

through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of

operation of the interface are shown in Table 7.3.

BCLKR

FSR

Interface Mode

64 kHz to 4.096 MHz 8 kHz

Long or Short Frame Sync

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

ISDN GCI with active channel B1

ISDN GCI with active channel B2

ISDN IDL with active channel B1

ISDN IDL with active channel B2

Table 7.3 PCM Interface mode selections

- 10 -

W6810

7.4.1. Long Frame Sync

The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the

BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8

kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC

sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when

the FST pin is held high for two consecutive falling edges of the bit-clock at the BCLKT pin. The length

of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge

occurs every 125 µsec. During data transmission in the Long Frame Sync mode, the transmit data pin

PCMT will become low impedance when the Frame Sync signal FST is high or when the 8 bit data

word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame

Sync signal FST becomes low while the data is transmitted or when half of the LSB is transmitted. The

internal decision logic will determine whether the next frame sync is a long or a short frame sync,

based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high

impedance for two frame sync cycles after every power down state. More detailed timing information

can be found in the interface timing section.

7.4.2. Short Frame Sync

The W6810 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is high

for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the

bit-clock, the W6810 starts clocking out the data on the PCMT pin, which will also change from high to

low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway

the LSB. The Short Frame Sync operation of the W6810 is based on an 8-bit data word. When

receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge

that coincides with the Frame Sync signal. The internal decision logic will determine whether the next

frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus

collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down

state. More detailed timing information can be found in the interface timing section.

7.4.3. General Circuit Interface (GCI)

The GCI interface mode is selected when the BCLKR pin is connected to V_SSfor two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface

consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects

channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data

clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.

The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted

consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is

transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.

Publication Release Date: October 10, 2002

- 11 -

Revision A9

W6810

7.4.4. Interchip Digital Link (IDL)

The IDL interface mode is selected when the BCLKR pin is connected to V_DDfor two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface

consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR

pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the

first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK

cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after

the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK

after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the

IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when

not used for data transmission and also in the time slot of the unused channel. For more timing

information, see the timing section.

7.4.5. System Timing

The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz

master clock rates. The system clock is supplied through the master clock input MCLK and can be

derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8

kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency

versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is low for

the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6810

will enter the low power standby mode. Another way to power down is to set the PUI pin to low. When

the system needs to be powered up again, the PUI pin needs to be set to high and the Frame Sync

pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low

impedance.

- 12 -

W6810

8. TIMING DIAGRAMS

T_FTRHM

T_FTRSM

T_{M CK L}

T_{M CK H}

T_RISE

T_{FA L L}

M CLK

T_{M CK}

T_FS

T_FSL

FST

T_FTRH

T_FTRS

T_FTFH

T_{BCK H}

T_{BCK L}

BCLK T

PCM T

0

1

2

3

4

5

6

7

8

0

1

T_FDTD

T_BDTD

T_HID

T_BCK

D7 D6 D5 D4 D3 D2 D1 D0

M SB LSB

T_FS

T_FSL

FSR

T_FRRH

T_FRRS

T_FRFH

T_{BCK H}

T_{BCK L}

BCLK R

PCM R

0

1

2

3

4

5

6

7

8

0

1

T_BCK

D7 D6 D5 D4 D3 D2 D1 D0

L SB

M SB

T_DRH

T_DRS

Figure 8.1 Long Frame Sync PCM Timing

Publication Release Date: October 10, 2002

Revision A9

- 13 -

W6810

SYMBOL

1/T_FS

T_FSL

1/T_BCK

T_BCKH

T_BCKL

DESCRIPTION

FST, FSR Frequency

MIN

---

T_BCK

64

50

TYP

8

MAX

---

UNIT

kHz

sec

kHz

ns

FST / FSR Minimum Low Width ¹

BCLKT, BCLKR Frequency

BCLKT, BCLKR High Pulse Width

BCLKT, BCLKR Low Pulse Width

---

4096

---

ns

T_FTRH

BCLKT 0 Falling Edge to FST Rising 20

Edge Hold Time

---

T_FTRS

T_FTFH

T_FDTD

T_BDTD

T_HID

FST Rising Edge to BCLKT 1 Falling 80

edge Setup Time

BCLKT 2 Falling Edge to FST Falling 50

Edge Hold Time

FST Rising Edge to Valid PCMT Delay ---

Time

BCLKT Rising Edge to Valid PCMT ---

Delay Time

---

60

ns

Delay Time from the Later of FST 10

Falling Edge, or

BCLKT 8 Falling Edge to PCMT Output

High Impedance

T_FRRH

T_FRRS

T_FRFH

T_DRS

BCLKR 0 Falling Edge to FSR Rising 20

Edge Hold Time

FSR Rising Edge to BCLKR 1 Falling 80

edge Setup Time

BCLKR 2 Falling Edge to FSR Falling 50

Edge Hold Time

---

ns

Valid PCMR to BCLKR Falling Edge

Setup Time

0

T_DRH

PCMR Hold Time from BCLKR Falling 50

Edge

Table 8.1 Long Frame Sync PCM Timing Parameters

¹T_FSLmust be at least ≥ T_BCK

- 14 -

W6810

T_FTRHM

T_FTRSM

T_{M CK L}

T_{M CK H}

T_RISE

T_{FA L L}

M CL K

T_{M CK}

T_FS

T_FTFH

T_FTFS

FST

T_FTRS

T_FTRH

T_{BCK H}

T_{BCK L}

BCL K T

PCM T

0

1

-1

0

1

2

3

4

5

6

7

8

T_BCK

T_BDTD

T_HID

D7 D6 D5 D4 D3 D2 D1 D0

M SB L SB

T_FS

T_FRFH

T_FRFS

FSR

T_FRRS

T_FRRH

T_{BCK H}

T_{BCK L}

BCL K R

PCM R

0

1

-1

0

1

2

3

4

5

6

7

8

T_BCK

D7 D6 D5 D4 D3 D2 D1 D0

M SB

L SB

T_DRH

T_DRS

Figure 8.2 Short Frame Sync PCM Timing

Publication Release Date: October 10, 2002

Revision A9

- 15 -

W6810

SYMBOL

1/T_FS

1/T_BCK

T_BCKH

T_BCKL

T_FTRH

DESCRIPTION

FST, FSR Frequency

BCLKT, BCLKR Frequency

BCLKT, BCLKR High Pulse Width

BCLKT, BCLKR Low Pulse Width

BCLKT –1 Falling Edge to FST Rising Edge Hold 20

Time

MIN

---

64

50

TYP

8

---

MAX

---

4096

---

UNIT

kHz

ns

T_FTRS

FST Rising Edge to BCLKT 0 Falling edge Setup 80

Time

---

ns

T_FTFH

T_FTFS

BCLKT 0 Falling Edge to FST Falling Edge Hold Time 50

FST Falling Edge to BCLKT 1 Falling Edge Setup 50

Time

---

ns

T_BDTD

T_HID

BCLKT Rising Edge to Valid PCMT Delay Time

Delay Time from BCLKT 8 Falling Edge to PCMT 10

Output High Impedance

10

---

60

ns

T_FRRH

T_FRRS

BCLKR –1 Falling Edge to FSR Rising Edge Hold 20

Time

FSR Rising Edge to BCLKR 0 Falling edge Setup 80

Time

---

ns

T_FRFH

T_FRFS

BCLKR 0 Falling Edge to FSR Falling Edge Hold Time 50

FSR Falling Edge to BCLKR 1 Falling Edge Setup 50

Time

---

ns

T_DRS

T_DRH

Valid PCMR to BCLKR Falling Edge Setup Time

PCMR Hold Time from BCLKR Falling Edge

0

50

---

ns

Table 8.2 Short Frame Sync PCM Timing Parameters

- 16 -

W6810

T_FS

FST

BCLK T

PCM T

T_FSFH

T_FSRS

T_FSRH

-1

T_{BCK H}

T_{BCK L}

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

T_BCK

T_BDTD

T_HID

T_BDTD

T_HID

T_BDTD

D7

D6 D5

D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2

M SB

D1 D0

L SB

M SB

L SB

T_DRS

T_DRH

T_DRS

T_DRH

D7

D6 D5

PCM R

D4 D3 D2 D1 D0

L SB

D7 D6 D5 D4 D3 D2

M SB

D1 D0

L SB

M SB

BCH = 0

BCH = 1

B1 Channel

B2 Channel

Figure 8.3 IDL PCM Timing

SYMBOL DESCRIPTION

MIN

---

256

50

TYP

8

---

MAX

---

4096

---

UNIT

kHz

ns

1/T_FS

1/T_BCK

T_BCKH

T_BCKL

T_FSRH

FST Frequency

BCLKT Frequency

BCLKT High Pulse Width

BCLKT Low Pulse Width

BCLKT –1 Falling Edge to FST Rising Edge 20

Hold Time

T_FSRS

T_FSFH

T_BDTD

T_HID

FST Rising Edge to BCLKT 0 Falling edge 60

Setup Time

BCLKT 0 Falling Edge to FST Falling Edge 20

Hold Time

BCLKT Rising Edge to Valid PCMT Delay 10

Time

Delay Time from the BCLKT 8 Falling Edge 10

(B1 channel) or BCLKT 18 Falling Edge (B2

Channel) to PCMT Output High Impedance

---

60

50

ns

T_DRS

T_DRH

Valid PCMR to BCLKT Falling Edge Setup 20

Time

PCMR Hold Time from BCLKT Falling Edge 75

Table 8.3 IDL PCM Timing Parameters

---

ns

Publication Release Date: October 10, 2002

Revision A9

- 17 -

W6810

T_FS

FST

BCL K T

PCM T

T_FSFH

T_FSRS

T_{BCK H}

T_{BCK L}

T_FSRH

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

T_HID

T_FDTD

D7

T_BDTD

D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

M SB

T_HID

T_BDTD

T_BCK

D6 D5

D1 D0

L SB

M SB

L SB

T_DRS

T_DRH

T_DRS

D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

M SB

T_DRH

D7

D6 D5

PCM R

D1 D0

L SB

M SB

L SB

BCH = 0

BCH = 1

B1 Channel

B2 Channel

Figure 8.4 GCI PCM Timing

SYMBOL

1/T_FST

1/T_BCK

T_BCKH

T_BCKL

T_FSRH

T_FSRS

T_FSFH

DESCRIPTION

FST Frequency

BCLKT Frequency

BCLKT High Pulse Width

BCLKT Low Pulse Width

MIN

---

512

50

20

TYP

8

MAX UNIT

---

kHz

---

6176 kHz

---

60

50

ns

BCLKT 0 Falling Edge to FST Rising Edge Hold Time

FST Rising Edge to BCLKT 1 Falling edge Setup Time 60

BCLKT 1 Falling Edge to FST Falling Edge Hold Time

FST Rising Edge to Valid PCMT Delay Time

BCLKT Rising Edge to Valid PCMT Delay Time

Delay Time from the BCLKT 16 Falling Edge (B1 10

channel) or BCLKT 32 Falling Edge (B2 Channel) to

PCMT Output High Impedance

20

---

T_FDTD

T_BDTD

T_HID

T_DRS

T_DRH

Valid PCMR to BCLKT Rising Edge Setup Time

PCMR Hold Time from BCLKT Rising Edge

Table 8.4 GCI PCM Timing Parameters

20

---

60

ns

- 18 -

W6810

SYMBOL

1/T_MCK

DESCRIPTION

Master Clock Frequency

MIN

TYP

256

MAX

---

UNIT

kHz

---

512

1536

1544

2048

2560

4096

T_MCKH

T_MCK

/

MCLK Duty Cycle for 256 kHz 45%

Operation

Minimum Pulse Width High for 50

MCLK(512 kHz or Higher)

Minimum Pulse Width Low for MCLK 50

(512 kHz or Higher)

MCLK falling Edge to FST Rising Edge 50

Hold Time

55%

---

T_MCKH

T_MCKL

T_FTRHM

T_FTRSM

---

ns

---

FST Rising Edge to MCLK Falling edge 50

Setup Time

---

T_RISE

T_FALL

Rise Time for All Digital Signals

Fall Time for All Digital Signals

---

50

ns

Table 8.5 General PCM Timing Parameters

Publication Release Date: October 10, 2002

Revision A9

- 19 -

W6810

9. ABSOLUTE MAXIMUM RATINGS

9.1. ABSOLUTE MAXIMUM RATINGS

Condition

Junction temperature

Value

150⁰C

-65⁰C to +150⁰C

Storage temperature range

Voltage Applied to any pin

(V_SS- 0.3V) to (V_DD+ 0.3V)

(V_SS– 1.0V) to (V_DD+ 1.0V)

300⁰C

Voltage applied to any pin (Input current limited to +/-20 mA)

Lead temperature (soldering – 10 seconds)

V_DD- V_SS

-0.5V to +6V

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability. Functional operation is not implied at these conditions.

9.2. OPERATING CONDITIONS

Condition

Industrial operating temperature

Value

-40⁰C to +85⁰C

Supply voltage (V_DD)

Ground voltage (V_SS)

+4.5V to +5.5V

0V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely

affect the life and reliability of the device.

- 20 -

W6810

10. ELECTRICAL CHARACTERISTICS

10.1. GENERAL PARAMETERS

Symbol Parameters

Conditions

Min ⁽²⁾Typ ⁽¹⁾

Max ⁽²⁾

Units

V_IL

Input Low Voltage

0.6

V

V_IH

V_OL

V_OH

Input High Voltage

2.4

PCMT Output Low Voltage

PCMT Output High Voltage

I_OL= 3 mA

0.4

I_OL= -3 mA

V_DD

–

0.4

5

8

mA

I_DD

I_SB

V_DDCurrent (Operating) - ADC + DAC

V_DDCurrent (Standby)

No Load

FST & FSR =V_ss;

PUI=V_DD

10

100

µA

I_pd

I_IL

V_DDCurrent (Power Down)

Input Leakage Current

PUI= V_ss

0.1

10

µA

V_SS<V_IN<V_DD

+/-10

V_SS<PCMT<V_DD

High Z State

I_OL

PCMT Output Leakage Current

C_IN

Digital Input Capacitance

10

15

pF

C_OUT

PCMT Output Capacitance

PCMT High Z

1. Typical values: T_A= 25°C , V_DD= 5.0 V

2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all

specifications are 100 percent tested.

Publication Release Date: October 10, 2002

- 21 -

Revision A9

W6810

10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS

V_DD=5V ±10%; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG;

PARAMETER SYM.

CONDITION

TYP.

TRANSMIT

RECEIVE

(D/A)

UNIT

(A/D)

MIN.

---

MAX.

MIN. MAX.

Absolute

Level

L_ABS

1.096

---

V_PK

0 dBm0 = 0dBm @ 600Ω

Max. Transmit T_XMAX

Level

1.579

1.573

---

V_PK

3.17 dBm0 for µ-Law

3.14 dBm0 for A-Law

Absolute Gain G_ABS

(0 dBm0 @

0 dBm0 @ 1020 Hz;

0

-0.25

+0.25

-0.25 +0.25

dB

T_A=+25°C

1020 Hz;

T_A=+25°C)

Absolute Gain G_ABST

variation with

0

-0.03

-0.05

+0.03

+0.05

-0.03 +0.03

-0.05 +0.05

dB

T_A=0°C to T_A=+70°C

T_A=-40°C to T_A=+85°C

Temperature

Frequency

G_RTV

15 Hz

50 Hz

60 Hz

200 Hz

300 to 3000 Hz

3300 Hz

3400 Hz

3600 Hz

4000 Hz

4600 Hz to 100 kHz

+3 to –40 dBm0

-40 to –50 dBm0

-50 to –55 dBm0

---

-1.0

-0.20

-0.35

-0.8

---

-0.3

-0.6

-1.6

-40

-30

-26

-0.4

+0.15

0

-14

-0.5

0

Response,

Relative to

0dBm0 @

1020 Hz

-0.20 +0.15

-0.35 +0.15

-0.8

---

0

---

-0.2

-0.4

-1.6

-14

-30

+0.2

+0.4

+1.6

-32

Gain Variation G_LT

vs. Level Tone

(1020 Hz

relative to –10

dBm0)

+0.3

+0.6

+1.6

dB

- 22 -

W6810

10.3. ANALOG DISTORTION AND NOISE PARAMETERS

V_DD=5V ±10%; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG;

PARAMETER

SYM.

CONDITION

TRANSMIT (A/D)

MIN. TYP. MAX.

RECEIVE (D/A)

MIN. TYP. MAX.

34

UNIT

dBC

Total Distortion vs.

Level Tone (1020 Hz,

µ-Law, C-Message

Weighted)

+3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

+3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

8400 Hz to 100000 Hz

300 to 3000 Hz

36

29

25

36

29

25

---

-47

---

D_LTµ

36

30

25

34

36

30

25

---

-30

-40

-30

-47

Total Distortion vs.

Level Tone (1020 Hz,

A-Law, Psophometric

Weighted)

D_LTA

dBp

dB

Spurious Out-Of-Band D_SPO

at RO- (300 Hz to

3400 Hz @ 0dBm0)

Spurious In-Band (700 D_SPI

Hz to 1100 Hz @

0dBm0)

Intermodulation

Distortion (300 Hz to

3400 Hz –4 to –21

dBm0

dB

D_IM

Two tones

---

-41

---

-41

Crosstalk (1020 Hz @ D_XT

0dBm0)

---

-75

---

-75

dBm0

Absolute Group Delay

1200Hz

360

240

µsec

τ_ABS

Group Delay

500 Hz

600 Hz

1000 Hz

2600 Hz

2800 Hz

---

750

380

130

750

5

---

750

370

120

750

13

τ_D

Distortion (relative to

group delay @ 1200

Hz)

Idle Channel Noise

N_IDL

dBrnc

dBm0p

µ-Law; C-message

A-Law; Psophometric

-69

-79

Publication Release Date: October 10, 2002

Revision A9

- 23 -

W6810

10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS

V_DD=5V ±10%; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG;

PARAMETER

AI Input Offset Voltage

AI Input Current

SYM.

V_OFF,AI

I_IN,AI

CONDITION

AI+, AI-

MIN.

---

TYP.

---

MAX.

±25

UNIT.

mV

AI+, AI-

---

±0.1

---

±1.0

---

µA

MΩ

pF

V

AI Input Resistance

AI Input Capacitance

AI Common Mode Input Voltage

Range

R_IN,AI

AI+, AI- to V_AG

AI+, AI-

10

---

1.2

C_IN,AI

V_CM,AI

---

10

V_DD-1.2

AI Common Mode Rejection

Ratio

CMRR_TIAI+, AI-

---

60

---

dB

AI Amp Gain Bandwidth Product GBW_TI

---

2150

95

---

kHz

dB

AO, R_LD≥10kΩ

C-Message Weighted

R_LD=10kΩ to V_AG

R_LD=2kΩ to V_AG

AO, RO to V_AG

AO, RO

AI Amp DC Open Loop Gain

AI Amp Equivalent Input Noise

AO Output Voltage Range

G_TI

N_TI

V_TG

---

0.5

1.0

-24

---

V_DD-0.5

V_DD-1.0

dBrnC

V

Load Resistance

R_LDTGRO

C_LDTGRO

I_OUT1

2

---

1

---

kΩ

pF

mA

Load Capacitance

---

±1.0

---

100

---

AO & RO Output Current

RO- Output Resistance

RO- Output Offset Voltage

Analog Ground Voltage

V_AGOutput Resistance

0.5 ≤AO,RO-≤ V_DD-0.5

RO-, 0 to 3400 Hz

RO- to V_AG

R_RO-

---

Ω

V_OFF,RO-

V_AG

R_VAG

---

mV

V

±25

2.573

12.5

Relative to V_SS

2.429 2.5

---

2.5

Within ±25mV change

Transmit

Receive

Ω

Power Supply Rejection Ratio (0 PSRR

to 100 kHz to V_DD, C-message)

30

---

80

75

---

dBC

PAI Input Offset Voltage

PAI Input Current

V_OFF,PAI

I_IN,PAI

PAI

mV

±20

PAI

---

10

---

±0.05 ±1.0

---

µA

PAI Input Resistance

R_IN,PAI

GBW_PI

PAI to V_AG

PAO- no load

---

MΩ

kHz

PAI Amp Gain Bandwidth

Product

1000

Output Offset Voltage

Load Resistance

V_OFF,PO

R_LDPO

PAO+ to PAO-

---

mV

±50

---

PAO+, PAO-

differentially

300

Ω

Load Capacitance

C_LDPO

PAO+, PAO-

differentially

---

1000

pF

- 24 -

W6810

PARAMETER

PO Output Current

SYM.

I_OUTPO

CONDITION

0.5 ≤AO,RO-≤ V_DD-0.5

PAO+ to PAO-

MIN.

±10.0

---

TYP.

---

1

MAX.

---

UNIT.

mA

PO Output Resistance

PO Differential Gain

R_PO

---

Ω

-0.2

0

+0.2

dB

G_PO

R_LD=300Ω, +3dBm0, 1

kHz, PAO+ to PAO-

PO Differential Signal to

45

---

60

40

---

dBC

dB

D_PO

Z_LD=300Ω

Distortion C-Message weighted

Z_LD=100nF + 100Ω

Z_LD=100nF + 20Ω

0 to 4 kHz

PO Power Supply Rejection

Ratio (0 to 25 kHz to V_DD,

Differential out)

40

---

55

40

---

PSRR_P

O

4 to 25 kHz

Publication Release Date: October 10, 2002

Revision A9

- 25 -

W6810

10.5. DIGITAL I/O

10.5.1. µ-Law Encode Decode Characteristics

Normalized

Encode

Decision

Levels

Digital Code

Decode

Levels

D7

D6

D5

D4

D3

D2

D1

D0

Sign

Chord

Step

0

Step

8159

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8031

:

7903

:

4319

1

4191

:

4063

:

2143

2079

:

2015

:

1055

1023

:

991

:

511

495

:

479

:

239

231

:

223

:

103

99

:

95

:

35

33

:

31

:

3

1

0

1

0

1

2

0

Notes:

Sign bit = 0 for negative values, sign bit = 1 for positive values

- 26 -

W6810

10.5.2. A-Law Encode Decode Characteristics

Normalized

Digital Code

Normalized

Encode

Decision

Levels

Decode

Levels

D7

D6

D5

D4

D3

D2

D1

D0

Sign

Chord

Step

4096

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4032

:

3968

:

2048

0

2112

:

2048

:

1088

1056

:

1024

:

544

528

:

512

:

272

264

:

256

:

136

132

:

128

:

68

66

:

64

:

2

0

1

Notes:

1. Sign bit = 0 for negative values, sign bit = 1 for positive values

2. Digital code includes inversion of all even number bits

Publication Release Date: October 10, 2002

Revision A9

- 27 -

W6810

10.5.3. PCM Codes for Zero and Full Scale

A-Law

Chord bits

(D6,D5,D4)

010

µ-Law

Chord bits

(D6,D5,D4) (D3,D2,D1,D0)

Level

Sign bit

(D7)

Step bits

Sign bit

(D7)

Step bits

(D3,D2,D1,D0)

1010

+ Full Scale

+ Zero

- Zero

1

0

000

111

000

0000

1111

0000

1

0

101

010

0101

1010

- Full Scale

10.5.4. PCM Codes for 0dBm0 Output

A-Law

Chord bits

(D6,D5,D4)

011

µ-Law

Sign bit Chord bits

Sample

Step bits

Sign bit

(D7)

0

Step bits

(D3,D2,D1,D0)

0100

(D7)

0

1

(D6,D5,D4) (D3,D2,D1,D0)

1

2

3

4

5

6

7

8

001

000

001

000

001

1110

1011

1110

1011

1110

0

1

010

011

010

011

0001

0100

0001

0100

- 28 -

W6810

11. TYPICAL APPLICATION CIRCUIT

0.01µF

µ

F

0.1

Ω

V_AUDIOIN+

1 V

2 RO-

3 PAI

4 PAO-

5 PAO+

V_AG20

AI+ 19

AI- 18

AO 17

µ/A 16

V_SS15

FST 14

PCMT 13

REF

27k

Ω

27k

27kΩ

1.0µF

-

V_AUDIOIN-

V_DD

V_AUDIOOUT

+

V_DD

6 V

DD

8 kHz

PCM OUT

2.048 MHz

0.1µF

7 FSR

8 PCMR

9 BCLKR BCLKT 12

10 PUI MCLK 11

Power

Control

PDIP/SOG/SSOP/TSSOP

PCM IN

Figure 11.1 Typical circuit for Differential Analog I/O’s

AUDIO OUT

R_L≥ 2kΩ

0.01µF

0.1µF

27kΩ

100µF

1 V_REF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 V_DD

V_AG20

AI+ 19

AI- 18

AO 17

µ/A 16

27kΩ

1.0 µF

AUDIO OUT

V_AUDIOIN

V_DD

R_L≥ 150Ω

V_DD

V_SS15

FST 14

PCMT 13

8 kHz

PCM OUT

2.048 MHz

0.1µF

7 FSR

8 PCMR

9 BCLKR BCLKT 12

10 PUI MCLK 11

PDIP/SOG/SSOP/TSSOP

Power

Control

PCM IN

Figure 11.2 Typical circuit for Single Ended Analog I/O’s

Publication Release Date: October 10, 2002

Revision A9

- 29 -

W6810

1kΩ

200 pF

Electret Microphone

WM -54B Panasonic

1.5k

µ

Ω

0.01 F

0.1µF

27kΩ

1 V_REF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 V_DD

V_AG20

AI+ 19

AI- 18

AO 17

µ/A 16

V_SS15

FST 14

27kΩ

100kΩ

1kΩ

1.0 µF

Speaker

V_DD

1.5k

Ω

V_DD

8 kHz

0.1µF

7 FSR

PCM OUT

2.048 MHz

8 PCMR

9 BCLKR BCLKT 12

PCMT 13

Power

10 PUI MCLK 11

Control

PDIP/SOG/SSOP/TSSOP

PCM IN

Figure 11.3 Handset Interface

0.01µF

27kΩ

0.1µF

27kΩ

1 V

2 RO-

3 PAI

4 PAO-

5 PAO+

6 V^DD

7 FSR

8 PCMR

9 BCLKR BCLKT 12

10 PUI

V_AG20

AI+ 19

AI- 18

AO 17

µ/A 16

TIP

REF

27kΩ

600Ω

1.0µF

600

27kΩ

N=

1

N=

1

Ω

V_DD

RI

NG

V

DD

V

^SS15

8 kHz

PCM OUT

4.096 MHz

0.1µF

FST 14

PCMT 13

Power

MCLK 11

Control

PDIP/SOG/SSOP/TSSOP

PCM IN

B1– 0V

B2- +5V

Figure 11.4 Transformer Interface Circuit in GCI mode

- 30 -

W6810

12. PACKAGE SPECIFICATION

12.1. 20L TSSOP - 4.4X6.5MM

PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS

DIMENSION (MM)

DIMENSION (INCH)

SYMBOL

MIN.

-

NOM.

MAX.

MIN.

-

NOM.

MAX.

0.047

0.006

0.041

0.177

A

A1

A2

E

-

1.20

0.15

1.05

4.50

-

0.05

0.80

4.30

-

0.002

0.031

0.169

-

0.035

0.90

4.40

0.173

HE

D

6.40 BSC

.252 BSC

0.256

6.40

0.50

6.50

6.60

0.75

0.252

0.020

0.260

0.030

L

0.60

0.024

L1

b

1.00 REF

0.039 REF

-

0.19

-

0.30

0.007

0.012

e

0.65 BSC

0.026 BSC

-

c

0.09

0º

-

0.20

8º

0.004

0º

0.008

8º

0

-

Y

0.10 BASIC

0.004 BASIC

Publication Release Date: October 10, 2002

Revision A9

- 31 -

W6810

12.2. 20L SOG (SOP)-300MIL

SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS

c

1

2

E

H

E

L

1

O

D

0.2

A

Y

SEATING PLANE

e

GAUGE

A

b

DIMENSION (MM)

DIMENSION (INCH)

SYMBOL

MIN.

2.35

0.10

0.33

0.23

7.40

12.60

MAX.

2.65

0.30

0.51

0.32

7.60

13.00

MIN.

0.093

0.004

0.013

0.009

0.291

0.496

MAX.

0.104

0.012

0.020

0.013

0.299

0.512

A

A1

b

c

E

D

e

1.27 BSC

0.050 BSC

H_E

Y

L

10.00

-

0.40

0º

10.65

0.10

1.27

8º

0.394

-

0.016

0º

0.419

0.004

0.050

8º

0

- 32 -

W6810

12.3. 20L SSOP-209 MIL

SHRINK SMALL OUTLINE PACKAGE

DIMENSIONS

D

1

2

DTEAIL A

H

E

1

b

A

SEATING PLANE

θ

L

Y

L

e

b

A

DETAIL A

DIMENSION (MM)

DIMENSION (INCH)

SYMBOL

MIN.

-

NOM.

MAX.

2.00

-

MIN.

-

NOM.

MAX.

A

A1

A2

b

-

0.079

-

0.05

1.65

0.22

0.09

6.90

5.00

7.40

-

0.002

0.065

0.009

0.004

0.272

0.197

0.291

-

0.069

-

1.75

-

1.85

0.38

0.25

7.50

5.60

8.20

-

0.015

0.010

0.295

0.220

0.323

-

c

-

D

7.20

5.30

7.80

0.65

0.75

1.25

-

0.283

0.209

0.307

0.0256

0.030

0.050

-

E

H_E

e

L

0.55

-

0.95

-

0.021

-

0.037

-

L1

Y

-

0.10

8º

-

0.004

8º

0

0º

-

0

-

Publication Release Date: October 10, 2002

Revision A9

- 33 -

W6810

12.4. 20L PDIP

PLASTIC DUAL INLINE PACKAGE DIMENSIONS

D

2

1

E

1

E

S

c

1

A

2

A

Base

A

Seating

L

B

e

₁

e

_A

á

B

₁

DIMENSION (MM)

DIMENSION (INCH)

SYMBOL

MIN.

-

NOM.

-

MAX.

4.45

-

MIN.

NOM.

-

MAX.

0.175

-

A

A₁

A₂

B

-

0.25

3918

0.41

1.47

0.20

-

0.010

0.125

0.016

0.058

0.008

-

3.30

0.46

1.52

0.25

20.06

7.62

6.35

2.54

3.30

-

3.43

0.56

1.63

0.36

26.42

7.87

6.48

2.79

3.56

15º

0.130

0.018

0.060

0.010

1.026

0.300

0.250

0.100

0.130

-

0.135

0.022

0.064

0.014

1.046

0.310

0.255

0.110

0.140

15º

B₁

c

D

E

7.37

6.22

2.29

3.05

0º

0.290

0.245

0.090

0.120

0º

E₁

e₁

L

á

e_A

S

8.51

-

9.02

-

9.53

1.91

0.335

-

0.355

-

0.375

0.075

- 34 -

W6810

13. ORDERING INFORMATION

Winbond Part Number Description

W6810I _

Package Type:

Product Family

W6810 Product

W

S

=

20-Lead Plastic Thin Small Outline Package (TSSOP) Type 1

20-Lead Plastic Small Outline Package (SOG/SOP)

20-Lead Plastic Small Outline Package (SSOP)

20-Lead Plastic Dual Inline Package (PDIP)

R

E

When ordering W6810 series devices, please refer to the following part numbers.

Part Number

W6810IW

W6810IS

W6810IR

W6810IE

Publication Release Date: October 10, 2002

Revision A9

- 35 -

W6810

14. VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A9

October

10, 2002

The information contained in this datasheet may be subject to change without

notice. It is the responsibility of the customer to check the Winbond USA website

(www.winbond-usa.com) periodically for the latest version of this document, and

any Errata Sheets that may be generated between datasheet revisions.

Headquarters

Winbond Electronics Corporation America

Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III

Science-Based Industrial Park,

Hsinchu, Taiwan

2727 North First Street, San Jose,

27F, 299 Yan An W. Rd. Shanghai,

CA 95134, U.S.A.

200336 China

TEL: 1-408-9436666

TEL: 86-21-62365999

FAX: 86-21-62356998

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 886-3-5665577

http://www.winbond-usa.com/

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation JapanWinbond Electronics (H.K.) Ltd.

9F, No. 480, Pueiguang Rd.

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Unit 9-15, 22F, Millennium City,

Neihu District,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Taipei, 114, Taiwan

TEL: 886-2-81777168

FAX: 886-2-87153579

TEL: 81-45-4781881

FAX: 81-45-4781800

Please note that all data and specifications are subject to change without notice.

All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

- 36 -

型号:	W6810IS
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4
针数：	20
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.64
压伸定律：	A/MU-LAW
滤波器：	YES
最大增益公差：	1.6 dB
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0
长度：	12.8 mm
功能数量：	1
端子数量：	20
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	2.65 mm
子类别：	Codecs
最大压摆率：	0.008 mA
标称供电电压：	5 V
表面贴装：	YES
电信集成电路类型：	PCM CODEC
温度等级：	INDUSTRIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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