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产品型号W681310SG的概述

W681310SG 芯片概述 W681310SG 是一款高性能的单片集成电路,主要用于实时处理和数据通信。该芯片由著名的半导体制造商设计并生产,广泛应用于各种电子设备中,例如智能手机、平板电脑、以及其他数字设备。它的设计目标是提供卓越的处理能力、较低的功耗和高效的数据传输能力,从而满足现代电子产品对性能与能效的苛刻要求。 详细参数 W681310SG 芯片的技术参数如下: - 工作电压:2.7V 至 3.6V - 工作温度范围:-40°C 至 +85°C - 处理器核心:8位微控制器,具有 RISC(精简指令集计算)架构 - 内存:支持高达 64KB 的 Flash 存储,8KB 的 SRAM - I/O 接口:提供多达 20 个通用输入输出(GPIO)引脚 - 通讯接口:SPI、I2C、UART等多种通讯协议 - 功耗:在待机状态下功耗低于 1μA - 工作频率:最高可达 20MHz...

产品型号W681310SG的Datasheet PDF文件预览

W681310  
3V SINGLE-CHANNEL VOICEBAND CODEC  
Data Sheet  
Publication Release Date: September 2005  
Revision B13  
- 1 -  
W681310  
1. GENERAL DESCRIPTION  
The W681310 is a general-purpose single channel PCM CODEC with pin-selectable μ-Law or A-Law  
companding. The device is compliant with the ITU G.712 specification. It operates from a single +3V  
power supply and is available in 20-pin SOG, SSOP and TSSOP package options. Functions  
performed include digitization and reconstruction of voice signals, and band limiting and smoothing  
filters required for PCM systems. W681310 performance is specified over the industrial temperature  
range of –40°C to +85°C.  
The W681310 includes an on-chip precision voltage reference and an additional power amplifier,  
capable of driving 300Ω loads differentially up to a level of 3.544V peak-to-peak. The analog section is  
fully differential, reducing noise and improving the power supply rejection ratio. The data transfer  
protocol supports both long-frame and short-frame synchronous communications for PCM  
applications, and IDL and GCI communications for ISDN applications. W681310 accepts eight master  
clock rates between 256 kHz and 4.800 MHz, and an on-chip pre-scaler automatically determines the  
division ratio for the required internal clock.  
For fast evaluation and prototyping purposes, the W681310DK development kit is available.  
ApplIcations  
2. FEATURES  
VoIP, Voice over Networks  
Single +3V power supply (2.7V to 5.25V)  
Digital telephone and communication  
systems  
Typical power dissipation of 10 mW,  
power-down mode of 0.5 μW  
Wireless voice devices  
PABX/SOHO systems  
Local loop card  
Fully-differential analog circuit design  
On-chip precision reference of 0.886 V for  
a -5 dBm TLP at 600 Ω  
SOHO routers  
Push-pull power amplifiers with external  
gain adjustment with 300 Ω load capability  
Fiber-to-curb equipment  
Enterprise phones  
ISDN equipment  
Eight master clock rates of 256 kHz to  
4.800 MHz  
Pin-selectable  
companding (compliant with ITU G.711)  
μ-Law  
and  
A-Law  
Modems/PC cards  
Digital Voice Recorders  
CODEC A/D and D/A filtering compliant  
with ITU G.712  
Industrial temperature range (–40°C to  
+85°C)  
Packages: 20-pin SOG (SOP), SSOP and  
TSSOP  
Pb-Free package options available  
- 2 -  
W681310  
3. BLOCK DIAGRAM  
BCLKR  
FSR  
PAO+  
PAO-  
PAI  
RO-  
AO  
PCMR  
G.712 CODEC  
BCLKT  
G.711 /A-Law  
μ
AI+  
AI-  
FST  
PCMT  
/A-Law  
μ
VREF  
256 kHz  
VAG  
MCLK  
Voltage reference  
Pre-Scaler  
8 kHz  
256 kHz,  
512 kHz,  
1536 kHz,  
1544 kHz,  
2048 kHz,  
2560 kHz  
4096 kHz  
Power Conditioning  
& 4800 kHz  
Publication Release Date: September 2005  
Revision B13  
- 3 -  
W681310  
4. TABLE OF CONTENTS  
1. GENERAL DESCRIPTION.................................................................................................................. 2  
2. FEATURES ......................................................................................................................................... 2  
3. BLOCK DIAGRAM .............................................................................................................................. 3  
4. TABLE OF CONTENTS ...................................................................................................................... 4  
5. PIN CONFIGURATION ....................................................................................................................... 6  
6. PIN DESCRIPTION............................................................................................................................. 7  
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8  
7.1. Transmit Path ................................................................................................................................8  
7.2. Receive Path .................................................................................................................................9  
7.3. Power Management.......................................................................................................................9  
7.3.1. Analog and Digital Supply.....................................................................................................10  
7.3.2. Analog Ground Reference Bypass .......................................................................................10  
7.3.3. Analog Ground Reference Voltage Outpt.............................................................................10  
7.4. PCM INTERFACE .......................................................................................................................10  
7.4.1. Long Frame Sync..................................................................................................................11  
7.4.2. Short Frame Sync .................................................................................................................11  
7.4.3. General Circuit Interface (GCI) .............................................................................................11  
7.4.4. Interchip Digital Link (IDL).....................................................................................................12  
7.4.5. System Timing ......................................................................................................................12  
8. TIMING DIAGRAMS.......................................................................................................................... 13  
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20  
9.1. Absolute Maximum Ratings.........................................................................................................20  
9.2. Operating Conditions...................................................................................................................20  
10. ELECTRICAL CHARACTERISTICS............................................................................................... 21  
10.1. General Parameters ..................................................................................................................21  
10.2. Analog Signal Level and Gain Parameters ...............................................................................22  
10.3. Analog Distortion and Noise Parameters ..................................................................................23  
10.4. Analog Input and Output Amplifier Parameters.........................................................................24  
10.5. DIGITAL I/O ...............................................................................................................................26  
10.5.1. μ-Law Encode Decode Characteristics...............................................................................26  
10.5.2. A-Law Encode Decode Characteristics ..............................................................................27  
10.5.3. PCM Codes for Zero and Full Scale ...................................................................................28  
10.5.4. PCM Codes for 0dBm0 Output ...........................................................................................28  
11. TYPICAL APPLICATION CIRCUIT................................................................................................. 29  
12. PACKAGE SPECIFICATION .......................................................................................................... 31  
- 4 -  
W681310  
12.1. 20L SOG (SOP)-300mil.............................................................................................................31  
12.2. 20L SSOP-209 mil.....................................................................................................................32  
12.3. 20L TSSOP - 4.4X6.5mm..........................................................................................................33  
13. ORDERING INFORMATION........................................................................................................... 34  
14. VERSION HISTORY ....................................................................................................................... 35  
Publication Release Date: September 2005  
- 5 -  
Revision B13  
W681310  
5. PIN CONFIGURATION  
VAG  
AI+  
AI-  
VREF  
RO-  
PAI  
PAO-  
PAO+  
VDD  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
3
AO  
4
SINGLE  
CHANNEL  
CODEC  
/A-Law  
5
μ
VSS  
6
FST  
FSR  
7
PCMT  
BCLKT  
MCLK  
PCMR  
BCLKR  
PUI  
8
9
10  
SOG/SSOP/TSSOP  
- 6 -  
W681310  
6. PIN DESCRIPTION  
Pin  
Name  
Pin Functionality  
No.  
VREF  
1
This pin is used to bypass the on-chip VDD/2 voltage reference. It needs to be decoupled to VSS  
through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin.  
RO-  
2
Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 0.886  
volt peak referenced to the analog ground level.  
PAI  
3
4
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.  
PAO-  
Inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially to  
1.772 volt peak referenced to the VAG voltage level.  
PAO+  
5
Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially  
to 1.772 volt peak referenced to the VAG voltage level.  
VDD  
6
7
Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.  
FSR  
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or  
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit  
and receive are synchronous operations.  
PCMR  
8
9
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.  
BCLKR  
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is  
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD  
.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.  
PUI  
10  
11  
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,  
the part is powered down.  
MCLK  
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544  
kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz. For a better performance, it is recommended  
to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in  
the case of 256 and 512 kHz frequency.  
BCLKT  
12  
PCM transmit bit clock input pin. This pin accepts clocks of 512 kHz to 6176 kHz in the GCI  
mode and 256 kHz to 4800kHz in all other PCM modes.  
PCMT  
FST  
13  
14  
15  
16  
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.  
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.  
This is the supply ground. This pin should be connected to 0V.  
VSS  
μ/A-Law  
Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law  
companding is selected when this pin is tied to VSS.  
AO  
AI-  
17  
18  
19  
20  
Analog output of the first gain stage in the transmit path.  
Inverting input of the first gain stage in the transmit path.  
Non-inverting input of the first gain stage in the transmit path.  
AI+  
VAG  
Mid-Supply analog ground pin, which supplies a VDD/2 volt reference voltage for all-analog  
signal processing. This pin should be decoupled to VSS with a 0.01μF capacitor. This pin  
becomes high impedance when the chip is powered down.  
Publication Release Date: September 2005  
- 7 -  
Revision B13  
W681310  
7. FUNCTIONAL DESCRIPTION  
W681310 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC  
complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a  
complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply  
with the specifications of the ITU-T G.711 recommendation.  
The block diagram in section 3 shows the main components of the W681310. The chip consists of a  
PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.  
The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate  
with the external frame sync frequency. The power conditioning block provides the internal power  
supply for the digital and the analog section, while the voltage reference block provides a precision  
analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in  
section 3.  
+
+
-
VAG  
PAO+  
+
-
PAO  
PAI  
Receive Path  
8
D/A  
-
RO  
Converter  
f
C
= 3400Hz  
Smoothing  
Smoothing  
/A-  
μ
Filter  
Filter  
Control  
Transmit Path  
AO  
AI+  
8
A/D  
+
Converter  
f
f
C
C  
= 3400Hz  
= 200Hz  
-
AI  
μ
-
/A  
High Pass Ant  
-Aliasing  
Ant-Aliasing  
Filter  
Control  
Filter  
Filter  
Figure 7.1 The W681310 Signal Path  
7.1. Transmit Path  
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain  
setting (see application examples in section 11). The device has an input operational amplifier whose  
output is the input to the encoder section. If the input amplifier is not required for operation it can be  
powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or  
the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The  
input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected as  
an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see  
Table 7.1).  
- 8 -  
W681310  
AI+  
Input Amplifier  
Input  
VDD  
Powered Down  
Powered Up  
AO  
1.2 to VDD-1.2  
VSS  
AI+, AI-  
AI-  
Powered Down  
Table 7.1 Input Amplifier Modes of operation  
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the  
analog ground voltage VAG  
.
The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent  
aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass  
filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to  
the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal  
is digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or  
A-Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression  
format can be selected according to Table 7.2.  
Format  
μ/A-Law Pin  
VSS  
VDD  
A-Law  
μ-Law  
Table 7.2. Pin-selectable Compression Format  
The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the  
sample rate supplied by the external frame sync FST.  
7.2. Receive Path  
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and  
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed  
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of  
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a  
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A  
sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered  
to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to  
provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external  
resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If  
the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDD  
.
7.3. POWER MANAGEMENT  
Publication Release Date: September 2005  
Revision B13  
- 9 -  
W681310  
7.3.1. Analog and Digital Supply  
The power supply for the analog and digital parts of the W681310 must be 2.7V to 5.25V. This supply  
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF  
ceramic capacitor.  
7.3.2. Analog Ground Reference Bypass  
The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog  
ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 μF ceramic  
capacitor.  
7.3.3. Analog Ground Reference Voltage Outpt  
The analog ground reference voltage is available for external reference at the VAG pin. This voltage  
needs to be decoupled to VSS through a 0.01 μF ceramic capacitor. The analog ground reference  
voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing.  
7.4. PCM INTERFACE  
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received  
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of  
operation of the interface are shown in Table 7.3.  
BCLKR  
FSR  
Interface Mode  
64 kHz to 4.800 MHz 8 kHz  
Long or Short Frame Sync  
VSS  
VSS  
VDD  
VDD  
VSS  
VDD  
VSS  
VDD  
ISDN GCI with active channel B1  
ISDN GCI with active channel B2  
ISDN IDL with active channel B1  
ISDN IDL with active channel B2  
Table 7.3 PCM Interface mode selections  
- 10 -  
W681310  
7.4.1. Long Frame Sync  
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR  
or BCLKT pin to a 64 kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8 kHz frame  
sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the  
positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is held  
HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync  
pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 μsec.  
During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low  
impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted.  
The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes  
LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will  
determine whether the next frame sync is a long or a short frame sync, based on the previous frame  
sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles  
after every power down state. More detailed timing information can be found in the interface timing  
section.  
7.4.2. Short Frame Sync  
The W681310 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH  
for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the  
bit-clock, the W681310 starts clocking out the data on the PCMT pin, which will also change from high  
to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway  
the LSB. The Short Frame Sync operation of the W681310 is based on an 8-bit data word. When  
receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that  
coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame  
sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions,  
the PCMT pin will be high impedance for two frame sync cycles after every power down state. More  
detailed timing information can be found in the interface timing section.  
7.4.3. General Circuit Interface (GCI)  
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame  
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface  
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects  
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock  
DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data  
rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively.  
Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the  
second 16 clock cycles of DCL. For more timing information, see the timing section. The GCI interface  
supports bit clocks of 512 kHz to 6176 kHz for data rates of 256 kHz to 3088 kHz.  
Publication Release Date: September 2005  
- 11 -  
Revision B13  
W681310  
7.4.4. Interchip Digital Link (IDL)  
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame  
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface  
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR  
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first  
positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle  
long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL  
SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL  
SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after  
the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data  
transmission and also in the time slot of the unused channel. For more timing information, see the  
timing section.  
7.4.5. System Timing  
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz, 4096 kHz &  
4800 kHz master clock rates. The system clock is supplied through the master clock input MCLK and  
can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz  
and 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency  
versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for  
the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681310  
will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When  
the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame Sync  
pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low  
impedance.  
- 12 -  
W681310  
8. TIMING DIAGRAMS  
TFTRHM  
TFTRSM  
TM CK L  
TM CK H  
TRISE  
TFA L L  
M CLK  
TM CK  
TFS  
TFSL  
FST  
TFTRH  
TFTRS  
TFTFH  
TBCK H  
TBCK L  
BCLK T  
PCM T  
0
1
2
3
4
5
6
7
8
0
1
TFDTD  
TBDTD  
THID  
THID  
TBCK  
D7 D6 D5 D4 D3 D2 D1 D0  
M SB LSB  
TFS  
TFSL  
FSR  
TFRRH  
TFRRS  
TFRFH  
TBCK H  
TBCK L  
BCLK R  
PCM R  
0
1
2
3
4
5
6
7
8
0
1
TBCK  
D7 D6 D5 D4 D3 D2 D1 D0  
L SB  
M SB  
TDRH  
TDRS  
Figure 8.1 Long Frame Sync PCM Timing  
Publication Release Date: September 2005  
Revision B13  
- 13 -  
W681310  
SYMBOL  
1/TFS  
DESCRIPTION  
MIN  
---  
TYP  
MAX UNIT  
FST, FSR Frequency  
8
---  
kHz  
sec  
1
TFSL  
FST / FSR Minimum Low Width  
BCLKT, BCLKR Frequency  
TBCK  
64  
1/TBCK  
TBCKH  
TBCKL  
---  
---  
---  
---  
4800 kHz  
BCLKT, BCLKR HIGH Pulse Width  
BCLKT, BCLKR LOW Pulse Width  
50  
---  
---  
---  
ns  
ns  
ns  
50  
TFTRH  
BCLKT 0 Falling Edge to FST Rising  
Edge Hold Time  
20  
TFTRS  
TFTFH  
TFDTD  
TBDTD  
THID  
FST Rising Edge to BCLKT 1 Falling  
edge Setup Time  
80  
50  
---  
---  
10  
---  
---  
---  
---  
---  
---  
---  
60  
60  
60  
ns  
ns  
ns  
ns  
ns  
BCLKT 2 Falling Edge to FST Falling  
Edge Hold Time  
FST Rising Edge to Valid PCMT Delay  
Time  
BCLKT Rising Edge to Valid PCMT  
Delay Time  
Delay Time from the Later of FST  
Falling Edge, or  
BCLKT 8 Falling Edge to PCMT Output  
High Impedance  
TFRRH  
TFRRS  
TFRFH  
TDRS  
BCLKR 0 Falling Edge to FSR Rising  
Edge Hold Time  
20  
80  
50  
0
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
ns  
ns  
ns  
ns  
ns  
FSR Rising Edge to BCLKR 1 Falling  
edge Setup Time  
BCLKR 2 Falling Edge to FSR Falling  
Edge Hold Time  
Valid PCMR to BCLKR Falling Edge  
Setup Time  
TDRH  
PCMR Hold Time from BCLKR Falling  
Edge  
50  
Table 8.1 Long Frame Sync PCM Timing Parameters  
1 TFSL must be at least TBCK  
- 14 -  
W681310  
TFTRHM  
TFTRSM  
TM CK L  
TM CK H  
TRISE  
TFA L L  
M CL K  
TM CK  
TFS  
TFTFH  
TFTFS  
FST  
TFTRS  
TFTRH  
TBCK H  
TBCK L  
BCL K T  
PCM T  
0
1
-1  
0
1
2
3
4
5
6
7
8
TBCK  
TBDTD  
TBDTD  
THID  
D7 D6 D5 D4 D3 D2 D1 D0  
M SB LSB  
TFS  
TFRFH  
TFRFS  
FSR  
TFRRS  
TFRRH  
TBCK H  
TBCK L  
BCLK R  
PCM R  
0
1
-1  
0
1
2
3
4
5
6
7
8
TBCK  
D7 D6 D5 D4 D3 D2 D1 D0  
M SB  
LSB  
TDRH  
TDRS  
Figure 8.2 Short Frame Sync PCM Timing  
Publication Release Date: September 2005  
Revision B13  
- 15 -  
W681310  
SYMBOL  
1/TFS  
DESCRIPTION  
MIN  
---  
TYP  
8
MAX UNIT  
FST, FSR Frequency  
---  
kHz  
1/TBCK  
TBCKH  
BCLKT, BCLKR Frequency  
BCLKT, BCLKR HIGH Pulse Width  
BCLKT, BCLKR LOW Pulse Width  
64  
50  
50  
20  
---  
---  
---  
---  
4800 kHz  
---  
---  
---  
ns  
ns  
ns  
TBCKL  
TFTRH  
BCLKT –1 Falling Edge to FST Rising Edge Hold  
Time  
TFTRS  
FST Rising Edge to BCLKT 0 Falling edge Setup  
Time  
80  
---  
---  
ns  
TFTFH  
TFTFS  
BCLKT 0 Falling Edge to FST Falling Edge Hold Time  
50  
50  
---  
---  
---  
---  
ns  
ns  
FST Falling Edge to BCLKT 1 Falling Edge Setup  
Time  
TBDTD  
THID  
BCLKT Rising Edge to Valid PCMT Delay Time  
10  
10  
---  
---  
60  
60  
ns  
ns  
Delay Time from BCLKT 8 Falling Edge to PCMT  
Output High Impedance  
TFRRH  
TFRRS  
BCLKR –1 Falling Edge to FSR Rising Edge Hold  
Time  
20  
80  
---  
---  
---  
---  
ns  
ns  
FSR Rising Edge to BCLKR 0 Falling edge Setup  
Time  
TFRFH  
TFRFS  
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time  
50  
50  
---  
---  
---  
---  
ns  
ns  
FSR Falling Edge to BCLKR 1 Falling Edge Setup  
Time  
TDRS  
TDRH  
Valid PCMR to BCLKR Falling Edge Setup Time  
PCMR Hold Time from BCLKR Falling Edge  
0
---  
---  
---  
---  
ns  
ns  
50  
Table 8.2 Short Frame Sync PCM Timing Parameters  
- 16 -  
W681310  
TFS  
FST  
BCL K T  
PCM T  
TFSFH  
TFSRS  
TFSRH  
-1  
TBCK H  
TBCK L  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18  
TBCK  
TBDTD  
THID  
TBDTD  
TBDTD  
THID  
TBDTD  
D7 D6 D5  
D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
M SB  
L SB  
M SB  
TDRS  
L SB  
TDRH  
TDRS  
TDRH  
D7  
PCM R  
D6 D5  
D4 D3 D2 D1 D0  
L SB  
D7 D6 D5 D4 D3 D2  
M SB  
D1 D0  
L SB  
M SB  
BCH = 0  
BCH = 1  
B1 Channel  
B2 Channel  
Figure 8.3 IDL PCM Timing  
SYMBOL DESCRIPTION  
MIN  
TYP  
8
MAX  
UNIT  
kHz  
kHz  
ns  
1/TFS  
1/TBCK  
TBCKH  
TBCKL  
TFSRH  
FST Frequency  
---  
256  
50  
---  
4800  
---  
BCLKT Frequency  
---  
---  
---  
---  
BCLKT HIGH Pulse Width  
BCLKT LOW Pulse Width  
50  
---  
ns  
BCLKT –1 Falling Edge to FST Rising Edge  
Hold Time  
20  
---  
ns  
TFSRS  
TFSFH  
TBDTD  
THID  
FST Rising Edge to BCLKT 0 Falling edge  
Setup Time  
60  
20  
10  
10  
---  
---  
---  
---  
---  
---  
60  
50  
ns  
ns  
ns  
ns  
BCLKT 0 Falling Edge to FST Falling Edge  
Hold Time  
BCLKT Rising Edge to Valid PCMT Delay  
Time  
Delay Time from the BCLKT 8 Falling Edge  
(B1 channel) or BCLKT 18 Falling Edge (B2  
Channel) to PCMT Output High Impedance  
TDRS  
TDRH  
Valid PCMR to BCLKT Falling Edge Setup  
Time  
20  
75  
---  
---  
---  
---  
ns  
ns  
PCMR Hold Time from BCLKT Falling Edge  
Table 8.3 IDL PCM Timing Parameters  
Publication Release Date: September 2005  
Revision B13  
- 17 -  
W681310  
TFS  
FST  
BCL K T  
PCM T  
TFSFH  
TFSRS  
TBCK H  
TBCK L  
TFSRH  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34  
THID  
TFDTD  
D7  
TBDTD  
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2  
M SB  
THID  
TBDTD  
TBDTD  
TBCK  
D6 D5  
D1 D0  
L SB  
M SB  
L SB  
TDRS  
TDRH  
TDRS  
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2  
M SB  
TDRH  
D7  
D6 D5  
PCM R  
D1 D0  
L SB  
M SB  
L SB  
BCH = 0  
BCH = 1  
B1 Channel  
B2 Channel  
Figure 8.4 GCI PCM Timing  
SYMBOL  
1/TFST  
1/TBCK  
TBCKH  
TBCKL  
DESCRIPTION  
MIN  
TYP  
8
MAX UNIT  
FST Frequency  
---  
512  
50  
50  
20  
60  
20  
---  
---  
kHz  
BCLKT Frequency  
BCLKT HIGH Pulse Width  
BCLKT LOW Pulse Width  
---  
---  
---  
---  
---  
---  
---  
---  
---  
6176 kHz  
---  
---  
---  
---  
---  
60  
60  
50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TFSRH  
TFSRS  
TFSFH  
BCLKT 0 Falling Edge to FST Rising Edge Hold Time  
FST Rising Edge to BCLKT 1 Falling edge Setup Time  
BCLKT 1 Falling Edge to FST Falling Edge Hold Time  
FST Rising Edge to Valid PCMT Delay Time  
TFDTD  
TBDTD  
THID  
BCLKT Rising Edge to Valid PCMT Delay Time  
---  
Delay Time from the BCLKT 16 Falling Edge (B1  
channel) or BCLKT 32 Falling Edge (B2 Channel) to  
PCMT Output High Impedance  
10  
TDRS  
TDRH  
Valid PCMR to BCLKT Rising Edge Setup Time  
PCMR Hold Time from BCLKT Rising Edge  
Table 8.4 GCI PCM Timing Parameters  
20  
---  
---  
---  
---  
ns  
ns  
60  
- 18 -  
W681310  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
256  
MAX  
UNIT  
1/TMCK  
Master Clock Frequency  
---  
---  
kHz  
512  
1536  
1544  
2048  
2560  
4096  
4800  
TMCKH  
TMCK  
/
MCLK Duty Cycle for 256 kHz  
Operation  
45%  
50  
55%  
---  
TMCKH  
TMCKL  
TFTRHM  
TFTRSM  
Minimum Pulse Width HIGH for  
MCLK(512 kHz or Higher)  
---  
---  
---  
---  
ns  
ns  
ns  
ns  
Minimum Pulse Width LOW for MCLK  
(512 kHz or Higher)  
50  
---  
MCLK falling Edge to FST Rising Edge  
Hold Time  
50  
---  
FST Rising Edge to MCLK Falling edge  
Setup Time  
50  
---  
TRISE  
TFALL  
Rise Time for All Digital Signals  
Fall Time for All Digital Signals  
---  
---  
---  
---  
50  
50  
ns  
ns  
Table 8.5 General PCM Timing Parameters  
Publication Release Date: September 2005  
Revision B13  
- 19 -  
W681310  
9. ABSOLUTE MAXIMUM RATINGS  
9.1. ABSOLUTE MAXIMUM RATINGS  
Condition  
Junction temperature  
Value  
1500C  
-650C to +1500C  
Storage temperature range  
Voltage Applied to any pin  
(VSS - 0.3V) to (VDD + 0.3V)  
(VSS – 1.0V) to (VDD + 1.0V)  
-0.5V to +6V  
Voltage applied to any pin (Input current limited to +/-20 mA)  
VDD - VSS  
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute  
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.  
9.2. OPERATING CONDITIONS  
Condition  
Industrial operating temperature  
Supply voltage (VDD  
Ground voltage (VSS)  
Value  
-400C to +850C  
)
+2.7V to +5.25V  
0V  
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely  
affect the life and reliability of the device.  
- 20 -  
W681310  
10. ELECTRICAL CHARACTERISTICS  
10.1. GENERAL PARAMETERS  
Symbol Parameters  
Conditions  
Min (2) Typ (1)  
Max (2)  
Units  
VIL  
Input LOW Voltage  
0.6  
V
V
V
V
VIH  
VOL  
VOH  
Input HIGH Voltage  
2.2  
PCMT Output LOW Voltage  
PCMT Output HIGH Voltage  
IOL = 1.6 mA  
0.4  
IOL = -1.6 mA  
VDD  
0.5  
VDD Current (Operating) - ADC + DAC  
VDD Current (Standby)  
3.3  
10  
5
mA  
IDD  
ISB  
No Load  
FST & FSR =Vss ;  
PUI=VDD  
100  
μA  
Ipd  
IIL  
VDD Current (Power Down)  
Input Leakage Current  
PUI= Vss  
0.1  
10  
μA  
μA  
μA  
VSS<VIN<VDD  
-10  
-10  
+10  
+10  
VSS<PCMT<VDD  
High Z State  
IOL  
PCMT Output Leakage Current  
CIN  
Digital Input Capacitance  
10  
15  
pF  
pF  
COUT  
PCMT Output Capacitance  
PCMT High Z  
1. Typical values: TA = 25°C , VDD = 3.0 V  
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications  
are 100 percent tested.  
Publication Release Date: September 2005  
- 21 -  
Revision B13  
W681310  
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS  
VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz;  
FST=FSR=8kHz Synchronous operation.  
PARAMETER SYM.  
CONDITION  
TYP.  
TRANSMIT  
(A/D)  
RECEIVE  
(D/A)  
UNIT  
MIN.  
---  
MAX.  
MIN.  
MAX.  
Absolute  
Level  
LABS  
0.616  
0.436  
---  
---  
---  
VPK  
VRMS  
0 dBm0 = -5dBm @ 600Ω  
Max. Transmit TXMAX  
Level  
0.8873 ---  
0.8843 ---  
---  
---  
---  
---  
---  
---  
VPK  
VPK  
3.17 dBm0 for μ-Law  
3.14 dBm0 for A-Law  
Absolute Gain GABS  
(0 dBm0 @  
1020 Hz;  
0 dBm0 @ 1020 Hz;  
TA=+25°C  
0
0
-0.20  
+0.20  
-0.20 +0.20  
dB  
TA=+25°C)  
Absolute Gain GABST  
variation with  
Temperature  
-0.05  
-0.10  
+0.05  
+0.10  
-0.05 +0.05  
-0.10 +0.10  
dB  
dB  
TA=0°C to TA=+70°C  
TA=-40°C to TA=+85°C  
Frequency  
Response,  
GRTV  
15 Hz  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
-40  
-0.5  
-0.5  
-0.5  
-0.5  
0
0
0
0
50 Hz  
---  
-30  
Relative to  
0dBm0 @  
1020 Hz  
60 Hz  
---  
-26  
200 Hz  
-1.4  
-0.15  
-0.35  
-0.8  
---  
-0.4  
+0.2  
+0.2  
+0.1  
0
300 to 3000 Hz  
3300 Hz  
-0.20 +0.2  
-0.4  
-0.8  
---  
+0.15  
0
3400 Hz  
3600 Hz  
0
4000 Hz  
---  
-14  
---  
-14  
-30  
+0.2  
+0.4  
+1.6  
4600 Hz to 100 kHz  
+3 to –40 dBm0  
-40 to –50 dBm0  
-50 to –55 dBm0  
---  
-32  
---  
Gain Variation GLT  
vs. Level Tone  
-0.3  
-0.6  
-1.6  
+0.3  
+0.6  
+1.6  
-0.2  
-0.4  
-1.6  
dB  
(1020 Hz  
relative to –10  
dBm0)  
- 22 -  
W681310  
10.3. ANALOG DISTORTION AND NOISE PARAMETERS  
VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz  
FST=FSR=8kHz Synchronous operation.  
PARAMETER  
SYM.  
CONDITION  
TRANSMIT (A/D)  
RECEIVE (D/A)  
MIN. TYP. MAX.  
UNIT  
MIN. TYP. MAX.  
Total Distortion vs.  
Level Tone (1020 Hz,  
μ-Law, C-Message  
Weighted)  
+3 dBm0  
34  
33.5  
30  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
34  
36  
30  
25  
30  
36  
34.2  
30  
15  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
dBC  
DLTμ  
0 dBm0 to -30 dBm0  
-40 dBm0  
-45 dBm0  
25  
Total Distortion vs.  
Level Tone (1020 Hz,  
A-Law, Psophometric  
Weighted)  
DLTA  
-3 dBm0  
30  
dBp  
dB  
-6 dBm0 to -27 dBm0  
-34 dBm0  
35  
34.5  
28.5  
13.5  
---  
-40 dBm0  
-55 dBm0  
Spurious Out-Of-Band DSPO  
at RO- (300 Hz to  
3400 Hz @ 0dBm0)  
4600 Hz to 7600 Hz  
7600 Hz to 8400 Hz  
8400 Hz to 100000 Hz  
300 to 3000 Hz  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
-30  
-40  
-30  
-47  
---  
---  
---  
---  
---  
Spurious In-Band (700 DSPI  
Hz to 1100 Hz @  
0dBm0)  
---  
-47  
---  
dB  
dB  
Intermodulation  
Distortion (300 Hz to  
3400 Hz –4 to –21  
dBm0  
DIM  
Two tones  
---  
---  
-41  
---  
---  
-41  
Crosstalk (1020 Hz @ DXT  
0dBm0)  
---  
---  
---  
---  
-75  
---  
---  
---  
---  
-75  
dBm0  
Absolute Group Delay  
1200Hz  
360  
240  
μsec  
μsec  
τABS  
Group Delay  
500 Hz  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
750  
380  
130  
130  
750  
19  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
750  
370  
120  
120  
750  
15  
τD  
Distortion (relative to  
group delay @ 1200  
Hz)  
600 Hz  
1000 Hz  
2600 Hz  
2800 Hz  
Idle Channel Noise  
NIDL  
dBrnc0  
dBm0p  
μ-Law; C-message  
-68  
-75  
A-Law; Psophometric  
Publication Release Date: September 2005  
Revision B13  
- 23 -  
W681310  
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS  
VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG  
;
PARAMETER  
AI Input Offset Voltage  
AI Input Current  
SYM.  
VOFF,AI  
IIN,AI  
CONDITION  
AI+, AI-  
MIN.  
---  
TYP.  
MAX.  
±25  
UNIT.  
---  
mV  
AI+, AI-  
---  
±0.1  
---  
±1.0  
---  
μA  
MΩ  
pF  
V
AI Input Resistance  
AI Input Capacitance  
RIN,AI  
AI+, AI- to VAG  
AI+, AI-  
10  
CIN,AI  
---  
---  
10  
AI Common Mode Input  
Voltage Range  
VCM,AI  
AI+, AI-  
1.2  
---  
VDD-1.2  
AI Common Mode Rejection  
Ratio  
CMRRTI AI+, AI-  
---  
---  
60  
---  
---  
dB  
AI Amp Gain Bandwidth  
Product  
GBWTI  
2150  
kHz  
AO, RLD10kΩ  
AI Amp DC Open Loop Gain  
GTI  
---  
---  
95  
-24  
---  
---  
---  
---  
1
---  
---  
dB  
AO, RLD10kΩ  
C-Message Weighted  
RLD=2kΩ to VAG  
AO, RO to VAG  
AO, RO  
AI Amp Equivalent Input Noise NTI  
dBrnC  
V
AO Output Voltage Range  
Load Resistance  
VTG  
0.4  
2
VDD-0.4  
---  
RLDTGRO  
CLDTGRO  
IOUT1  
kΩ  
pF  
Load Capacitance  
---  
200  
---  
AO & RO Output Current  
RO- Output Resistance  
RO- Output Offset Voltage  
Analog Ground Voltage  
mA  
0.5 AO,RO-VDD-0.5  
RO-, 0 to 3400 Hz  
RO- to VAG  
±1.0  
---  
RRO-  
---  
Ω
VOFF,RO-  
VAG  
---  
---  
mV  
V
±25  
Relative to VSS  
VDD/2-0.1 VDD/2 VDD/2+0.  
1
VAG Output Resistance  
RVAG  
---  
12.5  
25  
Within ±25mV change  
Transmit  
Ω
Power Supply Rejection Ratio PSRR  
(0 to 100 kHz to VDD, C-  
message)  
40  
40  
60  
60  
---  
---  
dBC  
Receive  
PAI Input Offset Voltage  
PAI Input Current  
VOFF,PAI  
IIN,PAI  
PAI  
---  
---  
10  
---  
---  
mV  
±25  
±1.0  
---  
PAI  
±0.05  
---  
μA  
PAI Input Resistance  
RIN,PAI  
GBWPI  
PAI to VAG  
PAO- no load  
MΩ  
kHz  
PAI Amp Gain Bandwidth  
Product  
1000  
---  
Output Offset Voltage  
VOFF,PO  
PAO+ to PAO-  
---  
---  
mV  
±50  
- 24 -  
W681310  
PARAMETER  
Load Resistance  
SYM.  
RLDPO  
CONDITION  
PAO+, PAO-  
MIN.  
300  
TYP.  
MAX.  
UNIT.  
---  
---  
Ω
differentially  
Load Capacitance  
CLDPO  
PAO+, PAO-  
differentially  
---  
---  
---  
1000  
---  
pF  
mA  
PAO Output Current  
IOUTPAO  
0.4 PAO+,PAO--VDD-  
0.4  
±6.0  
PAO Output Resistance  
PAO Differential Gain  
RPAO  
PAO+ to PAO-  
---  
1
0
---  
Ω
-0.2  
+0.2  
dB  
GPAO  
RLD=300Ω, +3dBm0, 1  
kHz, PAO+ to PAO-  
PAO Differential Signal to  
Distortion C-Message  
weighted  
45  
---  
---  
60  
40  
40  
---  
---  
---  
dBC  
dB  
DPAO  
ZLD=300Ω  
ZLD=100nF + 20Ω  
ZLD=100nF + 100Ω  
0 to 4 kHz  
PAO Power Supply Rejection  
40  
---  
55  
40  
---  
---  
PSRRP  
AO  
Ratio (0 to 25 kHz to VDD  
Differential out)  
,
4 to 25 kHz  
Publication Release Date: September 2005  
Revision B13  
- 25 -  
W681310  
10.5. DIGITAL I/O  
10.5.1. μ-Law Encode Decode Characteristics  
Normalized  
Normalized  
Encode  
Decision  
Levels  
Digital Code  
Decode  
Levels  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Sign  
Chord  
Chord  
Chord  
Step  
0
Step  
Step  
Step  
8159  
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
8031  
:
7903  
:
4319  
1
1
1
1
1
1
1
4191  
:
4063  
:
2143  
2079  
:
2015  
:
1055  
1023  
:
991  
:
511  
495  
:
479  
:
239  
231  
:
223  
:
103  
99  
:
95  
:
35  
33  
:
31  
:
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
Notes:  
Sign bit = 0 for negative values, sign bit = 1 for positive values  
- 26 -  
W681310  
10.5.2. A-Law Encode Decode Characteristics  
Normalized  
Digital Code  
Normalized  
Encode  
Decision  
Levels  
Decode  
Levels  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Sign  
Chord  
Chord  
Chord  
Step  
1
Step  
Step  
Step  
4096  
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032  
:
3968  
:
2048  
0
0
0
0
0
0
0
2112  
:
2048  
:
1088  
1056  
:
1024  
:
544  
528  
:
512  
:
272  
264  
:
256  
:
136  
132  
:
128  
:
68  
66  
:
64  
:
2
0
1
Notes:  
1. Sign bit = 0 for negative values, sign bit = 1 for positive values  
2. Digital code includes inversion of all even number bits  
Publication Release Date: September 2005  
Revision B13  
- 27 -  
W681310  
10.5.3. PCM Codes for Zero and Full Scale  
A-Law  
Chord bits  
(D6,D5,D4)  
010  
μ-Law  
Level  
Sign bit  
Chord bits  
Step bits  
Sign bit  
Step bits  
(D3,D2,D1,D0)  
1010  
(D7)  
(D6,D5,D4) (D3,D2,D1,D0)  
(D7)  
+ Full Scale  
+ Zero  
1
1
0
0
000  
111  
111  
000  
0000  
1111  
1111  
0000  
1
1
0
0
101  
0101  
- Zero  
101  
0101  
- Full Scale  
010  
1010  
10.5.4. PCM Codes for 0dBm0 Output  
A-Law  
Chord bits  
(D6,D5,D4)  
011  
μ-Law  
Sample  
Sign bit Chord bits  
Step bits  
Sign bit  
Step bits  
(D3,D2,D1,D0)  
0100  
(D7)  
0
(D6,D5,D4) (D3,D2,D1,D0)  
(D7)  
0
1
2
3
4
5
6
7
8
001  
000  
000  
001  
001  
000  
000  
001  
1110  
1011  
1011  
1110  
1110  
1011  
1011  
1110  
0
0
010  
0001  
0
0
010  
0001  
0
0
011  
0100  
1
1
011  
0100  
1
1
010  
0001  
1
1
010  
0001  
1
1
011  
0100  
- 28 -  
W681310  
11. TYPICAL APPLICATION CIRCUIT  
VDD  
0.1 uF  
U2  
27K  
17  
18  
19  
AO  
AI-  
AI+  
1.0 uF  
27K  
14  
12  
13  
8 KHz Frame Sy nc  
FST  
BCLKT  
PCMT  
-
DIFFERENTIAL  
AUDIO IN  
+
2.048 MHz  
Bit Clock  
27K  
11  
MCLK  
1.0 uF 27K  
20  
1
PCM OUT  
PCM IN  
VAG  
VREF  
8
9
7
PCMR  
BCLKR  
FSR  
2
3
4
5
RO-  
PAI  
0.01 uF  
27K  
27K  
0.1 uF  
16  
10  
MODE SELECT  
POWER CONTROL  
PAO-  
u/A  
PUI  
PAO+  
-
DIFFERENTIAL  
AUDIO OUT  
RL > 150 ohms  
W681310  
+
Figure 11.1 Typical circuit for Differential Analog I/O’s  
VDD  
0.1 uF  
U3  
27K  
17  
AO  
1.0 uF  
1.0 uF  
27K  
27K  
14  
12  
13  
8 KHz Frame Sync  
FST  
BCLKT  
PCMT  
18  
19  
AI-  
AUDIO IN  
2.048 MHz  
Bit Clock  
AI+  
27K  
11  
MCLK  
20  
1
PCM OUT  
PCM IN  
VAG  
VREF  
8
9
7
PCMR  
BCLKR  
FSR  
2
3
4
5
RO-  
PAI  
0.01 uF  
0.1 uF  
27K  
27K  
AUDIO OUT  
RL > 2K ohms  
16  
10  
MODE SELECT  
POWER CONTROL  
PAO-  
u/A  
PUI  
PAO+  
AUDIO OUT  
RL > 150 ohms  
100 uF  
W681310  
Figure 11.2 Typical circuit for Single Ended Analog I/O’s  
Publication Release Date: September 2005  
Revision B13  
- 29 -  
W681310  
VDD  
1.5K  
1K  
0.1 uF  
22 uF  
62k  
U4  
17  
18  
19  
AO  
AI-  
AI+  
+
1.0 uF 3.9K  
1.0 uF  
14  
12  
13  
8 KHz Frame Sy nc  
FST  
BCLKT  
PCMT  
100pF  
2.048 MHz  
Bit Clock  
3.9K  
100pF  
11  
MCLK  
ELECTRET  
MICROPHONE  
20  
1
PCM OUT  
PCM IN  
VAG  
VREF  
62K  
0.01 uF  
0.1 uF  
8
9
7
PCMR  
BCLKR  
FSR  
2
3
4
5
RO-  
PAI  
27K  
27K  
27K  
1.5K  
16  
10  
MODE SELECT  
POWER CONTROL  
PAO-  
u/A  
PUI  
PAO+  
W681310  
SPEAKER  
Figure 11.3 Handset Interface  
VDD  
0.1 uF  
U5  
27K  
17  
AO  
27K  
14  
12  
13  
8 KHz Frame Sync  
FST  
BCLKT  
PCMT  
18  
AI-  
4.096 MHz  
Bit Clock  
1.0 uF  
19  
AI+  
11  
MCLK  
20  
PCM OUT  
PCM IN  
VAG  
1
8
9
7
VREF  
27K  
PCMR  
BCLKR  
FSR  
600  
2
RO-  
0.01 uF  
TRANSFORMER  
600 OHM 1:1  
0.1 uF  
3
B1/B2 SELECT  
PAI  
27K  
4
16  
10  
MODE SELECT  
POWER CONTROL  
PAO-  
u/A  
PUI  
5
PAO+  
W681310  
Figure 11.4 Transformer Interface Circuit in GCI mode  
- 30 -  
W681310  
12. PACKAGE SPECIFICATION  
12.1. 20L SOG (SOP)-300MIL  
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS  
c
1
2
E
H
E
L
1
1
O
D
0 2  
A
Y
SEATING  
e
GAUGE  
A
b
DIMENSION (MM)  
DIMENSION (INCH)  
SYMBOL  
MIN.  
2.35  
0.10  
0.33  
0.23  
7.40  
12.60  
MAX.  
2.65  
0.30  
0.51  
0.32  
7.60  
13.00  
MIN.  
0.093  
0.004  
0.013  
0.009  
0.291  
0.496  
MAX.  
0.104  
0.012  
0.020  
0.013  
0.299  
0.512  
A
A1  
b
c
E
D
e
1.27 BSC  
0.050 BSC  
HE  
Y
10.00  
-
10.65  
0.10  
1.27  
8º  
0.394  
-
0.419  
0.004  
0.050  
8º  
L
0.40  
0º  
0.016  
0º  
0
Publication Release Date: September 2005  
Revision B13  
- 31 -  
W681310  
12.2. 20L SSOP-209 MIL  
SHRINK SMALL OUTLINE PACKAGE  
DIMENSIONS  
D
1
2
DTEAIL  
H
E
E
1
1
b
A
A
SEATING  
SEATING  
θ
L
Y
L
e
b
A
DETAIL  
DIMENSION (MM)  
DIMENSION (INCH)  
SYMBOL  
MIN.  
NOM.  
MAX.  
2.00  
-
MIN.  
NOM.  
MAX.  
0.079  
A
A1  
A2  
b
-
-
-
-
0.05  
1.65  
0.22  
0.09  
6.90  
5.00  
7.40  
-
-
0.002  
0.065  
0.009  
0.004  
0.272  
0.197  
0.291  
-
-
0.069  
-
-
1.75  
-
1.85  
0.38  
0.25  
7.50  
5.60  
8.20  
-
-
0.015  
0.010  
0.295  
0.220  
0.323  
-
c
-
-
D
7.20  
5.30  
7.80  
0.65  
0.75  
1.25  
-
0.283  
0.209  
0.307  
0.0256  
0.030  
0.050  
-
E
HE  
e
L
0.55  
-
0.95  
-
0.021  
-
0.037  
-
L1  
Y
-
0.10  
8º  
-
0.004  
8º  
0
0º  
-
0
-
- 32 -  
W681310  
12.3. 20L TSSOP - 4.4X6.5MM  
PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS  
DIMENSION (MM)  
DIMENSION (INCH)  
SYMBOL  
MIN.  
-
NOM.  
-
MAX.  
1.20  
MIN.  
-
NOM.  
-
MAX.  
A
A1  
A2  
E
0.047  
0.006  
0.041  
0.177  
0.05  
0.80  
4.30  
-
0.15  
1.05  
4.50  
0.002  
0.031  
0.169  
-
0.035  
0.90  
4.40  
0.173  
HE  
D
6.40 BSC  
.252 BSC  
0.256  
6.40  
0.50  
6.50  
6.60  
0.75  
0.252  
0.020  
0.260  
0.030  
L
0.60  
0.024  
L1  
b
1.00 REF  
0.039 REF  
-
0.19  
-
0.30  
0.007  
0.012  
e
0.65 BSC  
0.026 BSC  
-
c
0.09  
0º  
-
0.20  
8º  
0.004  
0º  
0.008  
8º  
0
-
-
Y
0.10 BASIC  
0.004 BASIC  
Publication Release Date: September 2005  
Revision B13  
- 33 -  
W681310  
13. ORDERING INFORMATION  
Winbond Part Number Description  
W681310_ _  
Product Family  
W681310 Product  
Package Material:  
Blank  
=
=
Standard Package  
Pb-free Package  
G
Package Type:  
S
R
=
=
=
20-Lead Plastic Small Outline Package (SOG/SOP)  
20-Lead Plastic Small Outline Package (SSOP)  
20-Lead Plastic Thin Small Outline Package (TSSOP)  
W
When ordering W681310 series devices, please refer to the following part numbers.  
Part Number  
W681310S  
W681310R  
W681310W  
W681310SG  
W681310RG  
W681310WG  
- 34 -  
W681310  
14. VERSION HISTORY  
VERSION  
A1  
DATE  
PAGE  
DESCRIPTION  
August 10, 2003  
August 22, 2003  
Draft version  
Update typo errors and parameters  
A2  
B11  
November,  
2004  
2
Added reference to TSSOP package and Pb-free  
packaging.  
6
Added reference to TSSOP package.  
Added description of TSSOP package.  
Added W and G package ordering code.  
Extended conditions on Table 10.2.  
33  
34  
22  
23  
Extended conditions on Table 10.3.  
Corrected Idle Channel Noise min/max and units.  
Improved Application Diagram  
Improved Application Diagram  
Add Important Notice  
B12  
B13  
April, 2005  
36  
29,30  
22  
September,  
2005  
Improved Application Diagram  
Added Reference to VRMS  
Capitalized logic HIGH/LOW  
Various  
Publication Release Date: September 2005  
- 35 -  
Revision B13  
W681310  
Important Notice  
Winbond products are not designed, intended, authorized or warranted for use as components  
in systems or equipment intended for surgical implantation, atomic energy control  
instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
instruments, combustion control instruments, or for other applications intended to support or  
sustain life. Further more, Winbond products are not intended for applications wherein failure  
of Winbond products could result or lead to a situation wherein personal injury, death or  
severe property or environmental damage could occur.  
Winbond customers using or selling these products for use in such applications do so at their  
own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
use or sales.  
The information contained in this datasheet may be subject to change without  
notice. It is the responsibility of the customer to check the Winbond USA website  
(www.winbond-usa.com) periodically for the latest version of this document, and  
any Errata Sheets that may be generated between datasheet revisions.  
Headquarters  
Winbond Electronics Corporation America  
Winbond Electronics (Shanghai) Ltd.  
No. 4, Creation Rd. III  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
2727 North First Street, San Jose,  
CA 95134, U.S.A.  
TEL: 1-408-9436666  
27F, 299 Yan An W. Rd. Shanghai,  
200336 China  
TEL: 86-21-62365999  
FAX: 86-21-62356998  
TEL: 886-3-5770066  
FAX: 1-408-5441798  
FAX: 886-3-5665577  
http://www.winbond-usa.com/  
http://www.winbond.com.tw/  
Taipei Office  
Winbond Electronics Corporation JapanWinbond Electronics (H.K.) Ltd.  
9F, No. 480, Pueiguang Rd.  
Neihu District,  
Taipei, 114, Taiwan  
TEL: 886-2-81777168  
FAX: 886-2-87153579  
7F Daini-ueno BLDG, 3-7-18  
Shinyokohama Kohoku-ku,  
Yokohama, 222-0033  
TEL: 81-45-4781881  
FAX: 81-45-4781800  
Unit 9-15, 22F, Millennium City,  
No. 378 Kwun Tong Rd.,  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
Please note that all data and specifications are subject to change without notice.  
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.  
- 36 -  
配单直通车
W681310SG产品参数
型号:W681310SG
是否Rohs认证: 符合
生命周期:Transferred
IHS 制造商:WINBOND ELECTRONICS CORP
零件包装代码:SOIC
包装说明:SOP, SOP20,.4
针数:20
Reach Compliance Code:unknown
HTS代码:8542.39.00.01
风险等级:5.32
压伸定律:A/MU-LAW
滤波器:YES
最大增益公差:1.6 dB
JESD-30 代码:R-PDSO-G20
JESD-609代码:e3
长度:12.8 mm
湿度敏感等级:3
功能数量:1
端子数量:20
工作模式:SYNCHRONOUS
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP20,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
电源:3/5 V
认证状态:Not Qualified
座面最大高度:2.65 mm
子类别:Codecs
最大压摆率:0.005 mA
标称供电电压:3 V
表面贴装:YES
电信集成电路类型:PCM CODEC
温度等级:INDUSTRIAL
端子面层:MATTE TIN
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:7.5 mm
Base Number Matches:1
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