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W681360

3V SINGLE-CHANNEL 13-BIT LINEAR VOICE-BAND CODEC

Data Sheet

Publication Release Date: September 2005

- 1 -

Revision A.2

W681360

1. GENERAL DESCRIPTION

The W681360 is a general-purpose single channel 13–bit linear PCM CODEC with 2s complement

data format. It operates from a single +3V power supply and is available in 20-pin SOG(SOP), SSOP

and TSSOP package options. The primary function of the device is the digitization and reconstruction

of voice signals, including the band limiting and smoothing required for PCM systems. The W681360

performance is specified over the industrial temperature range of –40°C to +85°C.

The W681360 includes an on-chip precision voltage reference. The analog section is fully differential,

reducing noise and improving the power supply rejection ratio. The V_AGreference pin allows for

decoupling of the internal circuitry that generates the reference voltage to the V_SSpower supply

ground, minimizing clock noise on the analog circuitry when external analog signals are referenced to

V_SS.

The data transfer protocol supports both long-frame and short-frame, synchronous and asynchronous

communications for PCM applications. The W681360 accepts eight master clock rates between

256kHz and 4.800MHz, and an on-chip pre-scaler automatically determines the division ratio for the

required internal clock.

An additional on-chip power amplifier is capable of driving 300Ω loads differentially up to a level of

3.544V peak-to-peak.

For fast evaluation a development kit (W681360DK) is available.

For fast prototyping purposes a low-cost evaluation board (W681360ES) is also available.

Applications

2. FEATURES

•

VoIP, Voice over Networks equipment

Digital telephone and communication

systems

•

Single +3V power supply (2.7V to 5.25V)

Typical power dissipation: 9.8mW

Standby power dissipation: 3µW

Power-Down dissipation: 0.09µW

Fully-differential analog circuit design for

low noise

•

Wireless Voice devices

DECT/Digital Cordless phones

Broadband Access Equipment

Bluetooth Headsets

Fiber-to-curb equipment

Enterprise phones

•

13-bit linear A/D & D/A conversions with 2s

complement data format

CODEC A/D and D/A filtering compliant

with ITU G.712

Digital Voice Recorders

Eight master clock rates of 256kHz to

4.800 MHz

256KHz – 4.8MHz bit clock rates on the

serial PCM port

On-chip precision reference of 0.886 V for

a -5 dBm TLP at 600 Ω (436mV_RMS

)

Programmable receive gain: 0 to –21dB in

3dB steps

•

Industrial temp. range (–40°C to +85°C)

20-pin SOG (SOP), SSOP and TSSOP as

well as a QFN-32L package

•

Pb-Free / RoHS package options available

Publication Release Date: September 2005

- 2 -

Revision A2

W681360

3. BLOCK DIAGRAM

BCLKR

PAO+

PAO-

PAI

FSR

PCMR

BCLKT

G.712 CODEC

RO-

AO

AI+

AI-

FST

PCMT

HB

V_AG

Voltage reference

256 kHz

8 kHz

MCLK

Pre-scaler

V_AGREF

256 kHz

512 kHz

1536 kHz

1544 kHz

2048 kHz

2560 kHz

4096 kHz

4800 kHz

Power Conditioning

Publication Release Date: September 2005

Revision A.2

- 3 -

W681360

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM............................................................................................................................... 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION............................................................................................................ 8

7.1. Transmit Path................................................................................................................................ 8

7.1.1 Input Operational Amplifier Gain............................................................................................. 9

7.2. Receive Path............................................................................................................................... 10

7.2.1. Receive Gain Adjust Mode................................................................................................... 11

7.3. Power Management.................................................................................................................... 11

7.3.1. Analog and Digital Supply.................................................................................................... 11

7.3.2. Analog Ground Reference Bypass ...................................................................................... 11

7.3.3. Analog Ground Reference Voltage Output .......................................................................... 11

7.4. PCM Interface............................................................................................................................. 12

7.4.1. Long Frame Sync................................................................................................................. 12

7.4.2. Short Frame Sync ................................................................................................................ 12

7.4.3. Special 16-bit Receive Modes.............................................................................................. 13

7.4.3.1. Sign-Extended Mode Timing............................................................................................. 13

7.4.3.2. Receive Gain Adjust Mode Timing.................................................................................... 13

7.4.4. System Timing ..................................................................................................................... 14

7.5. On-Chip Power Amplifier ............................................................................................................ 14

8. TIMING DIAGRAMS.......................................................................................................................... 15

9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20

9.1. Absolute Maximum Ratings........................................................................................................ 20

9.2. Operating Conditions.................................................................................................................. 20

10. ELECTRICAL CHARACTERISTICS............................................................................................... 21

10.1. General Parameters ................................................................................................................. 21

10.2. Analog Signal Level and Gain Parameters............................................................................... 22

10.3. Analog Distortion and Noise Parameters ................................................................................. 23

10.4. Analog Input and Output Amplifier Parameters........................................................................ 24

10.5. Digital I/O .................................................................................................................................. 26

10.5.1. PCM Codes for Zero and Full Scale .................................................................................. 26

10.5.2. PCM Codes for 1kHz Digital Milliwatt ................................................................................ 26

11. TYPICAL APPLICATION CIRCUIT................................................................................................. 27

12. PACKAGE DRAWING AND DIMENSIONS.................................................................................... 28

12.1. 20L SOG (SOP)-300mil............................................................................................................ 28

12.2. 20L SSOP-209 mil.................................................................................................................... 29

12.3. 20L TSSOP - 4.4X6.5mm......................................................................................................... 30

12.3. QFN-32L ................................................................................................................................... 31

Publication Release Date: September 2005

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Revision A.2

W681360

13. ORDERING INFORMATION........................................................................................................... 32

14. VERSION HISTORY ....................................................................................................................... 33

Publication Release Date: September 2005

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Revision A.2

W681360

5. PIN CONFIGURATION

V_AG

AI+

AI-

AO

HB

V_SS

FST

PCMT

BCLKT

MCLK

1

2

20

19

18

17

16

15

14

13

12

11

V_REF

RO-

PAI

PAO-

PAO+

V_DD

3

4

W681360

SINGLE

CHANNEL

5

6

7

FSR

CODEC

8

PCMR

BCLKR

PUI

9

10

SOG, SSOP,TSSOP

32 31 30 29 28 27 26

1

25

24

23

22

21

20

19

18

17

NC

RO-

2

3

4

5

6

7

8

9

AI-

PAI

AO

PAO-

HB

NC

V_SS

FST

NC

PAO+

V_DD

FSR

PCMR

NC

PCMT

BCLKR

10 11 12 13 14 15 16

QFN-32L

Publication Release Date: September 2005

Revision A.2

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W681360

6. PIN DESCRIPTION

Name

Pin No.

Functionality

non-

QFN

V_REF

1

30

This pin is used to bypass the on–chip V_DD/2 voltage reference for the V_AGoutput pin.

This pin should be bypassed to V_SSwith a 0.1μF ceramic capacitor using short, low

inductance traces. The V_REFpin is only used for generating the reference voltage for the

V_AGpin. Nothing is to be connected to this pin except the bypass capacitor.

Inverting output of the receive smoothing filter. This pin can typically drive a 2kΩ load to

0.886V_PEAKreferenced to analog ground.

RO-

2

3

4

5

1

2

3

5

PAI

Inverting input to the power amplifier. The non-inverting input is tied internally to V_AG

voltage.

PAO-

PAO+

Inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially

to 1.772V_PEAK

.

Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load

differentially to 1.772V_PEAK

.

V_DD

FSR

6

7

6

7

Power supply. Should be decoupled to V_SSwith a 0.1μF ceramic capacitor.

8kHz Frame Sync input for the PCM receive section. FSR can be asynchronous to FST in

either Long Frame Sync or Short Frame Sync mode.

PCMR

8

9

8

9

PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR

pins.

BCLKR

PCM receive bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz.

When not clocked it can be used to select the 16 sign-bit extended synchronous mode

(BCLKR=0) or the receive gain adjust synchronous mode (BCLKR=1)

Power up input signal. When this pin is tied to V_DD, the part is powered up. When tied to

V_SS, the part is powered down.

System master clock input. Possible input frequencies are 256kHz, 512kHz, 1536kHz,

1544kHz, 2048kHz, 2560kHz, 4096kHz & 4800kHz. For performance reasons, it is

recommended that MCLK be synchronous and aligned to the FST signal. This is a

requirement in the case of 256 and 512kHz frequencies.

PUI

10

11

12

13

MCLK

BCLKT

PCMT

12

13

16

17

PCM transmit bit clock input pin. Can accept any bit clock frequency from 256 to

4800kHz.

PCM output data transmit pin. The output data is synchronous with the FST and BCLKT

pins.

FST

V_SS

HB

14

15

16

19

20

22

8kHz transmit frame sync input. This pin synchronizes the transmit data bytes.

This is the supply ground. This pin should be connected to 0V.

High-pass Bypass. Determines if the transmit high-pass filter is used (HB=’0’) or

bypassed (HB=’1’). When the high pass is bypassed the frequency response extends to

DC.

AO

AI-

AI+

V_AG

17

18

19

20

23

24

26

29

Analog output of the first gain stage in the transmit path.

Inverting input of the first gain stage in the transmit path.

Non-inverting input of the first gain stage in the transmit path.

Mid-Supply analog ground pin, which supplies a V_DD/2 volt reference voltage for all-

analog signal processing. This pin should be decoupled to V_SSwith a 0.01μF capacitor.

This pin becomes high impedance when the chip is powered down.

Publication Release Date: September 2005

- 7 -

Revision A.2

W681360

7. FUNCTIONAL DESCRIPTION

W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC

complies with the specifications of the ITU-T G.712 recommendation.

The CODEC block diagram in Section 3 illustrates the main components of the W681360. The chip

consists of a PCM interface, which can process long and short frame sync formats. The pre-scaler of

the chip provides the internal clock signals and synchronizes the CODEC sample rate with the

external frame sync frequency. The power conditioning block provides the internal power supply for

the digital and the analog section, while the voltage reference block provides a precision analog

ground voltage for the analog signal processing.

The calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog

Converter (DAC) is referenced to μ-Law with the same bit voltage weighing about the zero crossing,

resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based

on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600Ω.

VAG

+

-

PAO+

PAO-

+

PAI

13

13 bit linear

DAC

DATA

Receive

Buffer1

Av=1

RO-

f_C= 3400 Hz

Smoothing

Filter b

Smoothing

Filter a

High Pass

Bypass

AO

13

AI-

-

13 bit linear

ADC

DATA

AI+

Transmit

+

f_C= 200 Hz

f_C= 3400 Hz

High Pass

Filter

Anti-Aliasing

Filter a

Anti-Aliasing

Filter b

FIGURE 7.1: THE W681360 SIGNAL PATH

7.1. Transmit Path

The first stage of the A-to-D path of the CODEC is an analog input operational

amplifier with externally configurable gain settings. A differential analog input may be

applied to the Inputs AI+ and AI-. Alternately the input amplifier may be powered

down and a single-ended input signal can be applied to either the AO pin or the AI-

pin. The input amplifier can be powered down by connecting the AI+ pin to either V_DD

or V_SSwhich also determines whether AO or AI+ is selected as input according to

Publication Release Date: September 2005

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Revision A.2

W681360

Table 7.1. When the input operational amplifier is powered down the AO pin becomes high input

impedance.

TABLE 7.1: INPUT AMPLIFIER MODES OF OPERATION

AI+ (Pin 19)

Input Amplifier

Input

V_DD

1.2 to V_DD-1.2

V_SS

Powered Down

Powered Up

Powered Down

AO (Pin 17)

AI+, AI- (Pins 19, 18)

AI- (Pin 18)

When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the

analog ground voltage V_AG.

The output of the input operational amplifier is first fed through a low-pass filter to prevent aliasing at

the switched capacitor 3.4kHz low pass filter. Subsequently the 3.4kHz switched capacitor low pass

filter bandlimits the input signals well below 4kHz. Signals above 4kHz would be aliased at the

sampling rate of 8kHz. A high pass filter with a 200Hz cut-off frequency prevents DC coupling. All

filters are designed according to the G.712 ITU-T specification. The high-pass filter may be bypassed

depending on the logic level on the HB pin. If the high pass is removed the frequency response of the

device extends down to DC.

After filtering the signal is digitized as a 13-bit linear PCM code and fed to the PCM interface for serial

transmission at the sample rate supplied by the external frame sync FST.

7.1.1 Input Operational Amplifier Gain

The gain of the input operational amplifier can be adjusted using external resistors. For single-ended

input operation the gain is given by a simple resistive ratio.

FIGURE 7.2: INPUT OPERATIONAL AMPLIFIER GAIN – SINGLE-ENDED INPUT

Ro

AO

AI-

Ri

Vin

VAG

-

+

AI+

Gin = Ro/Ri

For differential input operation the external resistor network is more complex but the gain is expressed

in the same way. Of course, a differential input also has an inherent 6dB advantage over a

corresponding single-ended input.

Publication Release Date: September 2005

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Revision A.2

W681360

Ro

AO

AI-

Ri

Vin-

-

+

Vin+

AI+

Ro

Gin = Ro/Ri

VAG

FIGURE 7.3: INPUT OPERATIONAL AMPLIFIER GAIN – DIFFERENTIAL INPUT

The gain of the operational amplifier will be typically be set to 30dB for microphone interface circuits.

However the gain may be used for more than 30dB but this will require a compact layout with minimal

trace lengths and good isolation from noise sources. It is also recommended that the layout be as

symmetrical as possible as imbalances work against the noise canceling advantages of the differential

design.

7.2. Receive Path

The 13-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and

converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed

through the 13-bit linear DAC and converted to analog samples. The analog samples are filtered by a

low-pass smoothing filter with a 3.4kHz cut-off frequency, according to the ITU-T G.712 specification.

A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is

buffered to provide the receive output signal RO-. The output may be also be attenuated when the

device is in the receive path adjust mode. If the device is operated half–channel with the FST pin

clocking and FSR pin held LOW, the receive filter input will be connected to the V_AGvoltage. This

minimizes transients at the RO– pin when full–channel operation is resumed by clocking the FSR pin.

The RO- output can be externally connected to the PAI pin to provide a differential output with high

driving capability at the PAO+ and PAO- pins. By using external resistors various gain settings of this

output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down

by connecting PAI to V_DD. The bias voltage and signal reference of the PAO+ & PAO– outputs is the

V_AGpin. The V_AGpin cannot source or sink as much current as these pins, and therefore low

impedance loads must be placed between PAO+ and PAO–. The PAO+ and PAO– differential drivers

are also capable of driving a 100Ω resistive load or a 100nF piezoelectric transducer in series with a

20Ω resister with a small increase in distortion. These drivers may be used to drive resistive loads of

32Ω when the gain of PAO– is set to 1/4 or less.

Publication Release Date: September 2005

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Revision A.2

W681360

7.2.1. Receive Gain Adjust Mode

The W681360 can be put in the receive path adjust mode by applying a logic “1” to the BCLKR pin

while all other clocks are clocked normally. The device is then in a position to read 16-bits of data,

with three additional coefficient bits an addend to the 13-bit digital voice data. These three coefficients

are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated

according to the values in the following table. If the feature is not used the default value is 0dB.

TABLE 7.2: ATTENUATION COEFFICIENT RELATIONSHIP IN RECEIVE GAIN ADJUST MODE

Coefficient

Attenuation (dB)

000

001

010

011

100

101

110

111

0

3

6

9

12

15

18

21

7.3. POWER MANAGEMENT

7.3.1. Analog and Digital Supply

The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply

voltage is connected to the V_DDpin. The V_DDpin needs to be decoupled to ground through a 0.1 μF

ceramic capacitor.

7.3.2. Analog Ground Reference Bypass

The system has an internal precision voltage reference which generates the V_DD/2 mid-supply analog

ground voltage. This voltage needs to be decoupled to V_SSat the V_REFpin through a 0.1 μF ceramic

capacitor.

7.3.3. Analog Ground Reference Voltage Output

The analog ground reference voltage is available for external reference at the V_AGpin. This voltage

needs to be decoupled to V_SSthrough a 0.01 μF ceramic capacitor. The analog ground reference

voltage is generated from the voltage on the V_REFpin and is also used for the internal signal

processing.

Publication Release Date: September 2005

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Revision A.2

W681360

7.4. PCM INTERFACE

The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received

through the PCMR pin and the output data is transmitted through the PCMT pin.

The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR

or BCLKT pin to a 256kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8kHz frame

sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on

the positive edge of the Frame Sync signal. Long Frame Sync is recognized when the FST pin is held

HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. Short Frame Sync Mode is

recognized when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the

bit-clock at the BCLKT pin.

7.4.1. Long Frame Sync

The device recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling

edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to

frame, as long as the positive frame sync edge occurs every 125 μsec. During data transmission in the

Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame

Sync signal FST is HIGH or when the 13-bit data word is being transmitted. The transmit data pin

PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is

transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether

the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid

bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down

state. Long Frame Sync mode is illustrated below. More detailed timing information can be found in

the interface timing section.

BCLKT

(BCLKR)

FST

(FSR)

PCMT

1

2

3

4

5

6

7

8

9

10 11 12 13

PCMR don't care

10 11 12 13 don't care

Long Frame Sync (Transmit and Receive Have Individual Clocking)

FIGURE 7.4: LONG FRAME SYNC PCM MODE

7.4.2. Short Frame Sync

The W681360 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is

HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge

of the bit-clock, the W681360 starts clocking out the data on the PCMT pin, which will also change

from high to low impedance state. The data transmit pin PCMT will go back to the high impedance

state halfway through the LSB. The Short Frame Sync operation of the W681360 is based on a 13-bit

data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after

the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine

whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.

To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every

power down state. Short Frame Sync mode is illustrated below. More detailed timing information can

be found in the interface timing section.

Publication Release Date: September 2005

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Revision A.2

W681360

BCLKT

(BCLKR)

FST

(FSR)

PCMT

1

2

3

4

5

6

7

8

9

10 11 12 13

PCMR don't care

10 11 12 13 don't care

Short Frame Sync (Transmit and Receive Have Individual Clocking)

FIGURE 7.5: SHORT FRAME SYNC PCM MODE

7.4.3. Special 16-bit Receive Modes

7.4.3.1. Sign-Extended Mode Timing

The Sign-bit extended mode is entered by applying a logic “0” to the BCLKR pin while all other clocks

are clocked normally. In standard 13-bit mode the first bit is the sign bit. In this mode the device

transmits and receives 16-bit data where the sign bit is extended to the first four data bits. The PCM

timing for this mode is illustrated below.

BCLKT

(BCLKR)

FST (FSR)

SHORT OR

LONG FRAME

SYNC

PCMT

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

PCMR don't care

10 11 12 13 14 15 16 don't care don't care

Sign-Extended (BCLKR=0)

Transmit and Receive both use BCLKT, and the first four data bits are the sign bit.

FST may occur at a different time than FSR

FIGURE 7.6: SIGN EXTENDED MODE

7.4.3.2. Receive Gain Adjust Mode Timing

The Receive Path Adjust Mode is entered by applying a logic “1” to the BCLKR pin while all other

clocks are clocked normally. In this mode the device receives 16-bit data where the last three bits are

coefficients to program the Receive Gain Adjust Attenuation described above. The PCM timing for

this mode is illustrated below.

Publication Release Date: September 2005

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Revision A.2

W681360

BCLKT

(BCLKR)

FST (FSR)

SHORT OR

LONG FRAME

SYNC

PCMT

1

2

3

4

5

6

7

8

9

10 11 12 13

PCMR don't care

10 11 12 13 14 15 16 don't care don't care

Receive Gain Adjust (BCLKR=1)

Transmit and Receive both use BCLKT. FST may occur at a different time than FSR.

Bits 14, 15, and 16, clocked into PCMR, are used for attenuation control for the

receive analog output.

FIGURE 7.7: RECEIVE GAIN ADJUST TIMING MODE

7.4.4. System Timing

The system can work at 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz &

4800kHz master clock rates. The system clock is supplied through the master clock input MCLK and

can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256kHz

and 8kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency

versus the Frame Sync frequency and sets the division ratio accordingly. If both Frame Syncs are

LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the

W681360 will enter the low power standby mode. Another way to power down is to set the PUI pin to

LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the

transmit Frame Sync pulse needs to be present. It will take two transmit Frame Sync cycles before the

pin PCMT becomes low impedance.

7.5. ON-CHIP POWER AMPLIFIER

The on-chip power amplifier is typically used to drive an external loudspeaker. The inverting input to

the power amplifier is available at pin PAI. The non-inverting input is tied internally to V_AG.The

inverting output PAO– is used to provide a feedback signal to the PAI pin to set the gain of the power

amplifier outputs (PAO+ and PAO-). These push–pull outputs are capable of driving a 300Ω load to

1.772 V_PEAK

.

Connecting PAI to V_DDwill power down the power driver amplifiers and the PAO+ and PAO– outputs

will be high impedance.

Publication Release Date: September 2005

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Revision A.2

W681360

8. TIMING DIAGRAMS

T_FTRHM

T_MCK

T_RISE

T_FTRSM

T_FALL

MCLK

T_MCKH

T_MCKL

T_BCK

BCLKT

T_FTRS

T_FTRH

T_BCKH

T_FTFH

T_BCKL

T_FS

T_FSL

FST

T_FDTD

T_BDTD

T_HID

T_FDTD

T_HID

PCMT

MSB

LSB

T_BCK

BCLKR

(BCLKT)

T_FRRS

T_FRRH

T_BCKH

T_FRFH

T_BCKL

FSR

T_DRS

PCMR

T_DRH

MSB

LSB

FIGURE 8.1: LONG FRAME SYNC PCM TIMING

NOTE: The Data is clocked out on the rising edge of BCLK.

The Data is clocked in on the falling edge of BCLK.

Publication Release Date: September 2005

Revision A.2

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W681360

TABLE 8.1: LONG FRAME SYNC PCM TIMING PARAMETERS

SYMBOL

1/T_FS

T_FSL

1/T_BCK

T_BCKH

T_BCKL

DESCRIPTION

MIN

TYP

MAX

---

UNIT

kHz

sec

kHz

ns

FST, FSR Frequency

---

T_BCK

256

50

20

8

FST / FSR Minimum LOW Width ¹

1

BCLKT, BCLKR Frequency

---

4800

---

BCLKT, BCLKR HIGH Pulse Width

BCLKT, BCLKR LOW Pulse Width

BCLKT Falling Edge to FST Rising

Edge Hold Time

ns

T_FTRH

---

T_FTRS

T_FTFH

T_FDTD

FST Rising Edge to BCLKT Falling

edge Setup Time

BCLKT Falling Edge to FST Falling

Edge Hold Time

The later of BCLKT rising edge, or FST

rising edge to first valid PCMT Bit Delay

Time

80

50

---

60

ns

T_BDTD

T_HID

BCLKT Rising Edge to Valid PCMT

Delay Time

Delay Time from the Later of FST

Falling Edge, or

---

60

ns

10

BCLKT Falling Edge of last PCMT Bit to

PCMT Output High Impedance

BCLKR Falling Edge to FSR Rising

Edge Hold Time

FSR Rising Edge to BCLKR Falling

edge Setup Time

BCLKR Falling Edge to FSR Falling

Edge Hold Time

Valid PCMR to BCLKR Falling Edge

Setup Time

T_FRRH

T_FRRS

T_FRFH

T_DRS

20

80

50

1

---

ns

T_DRH

PCMR Hold Time from BCLKR Falling

Edge

50

¹T_FSLmust be at least ≥ T_BCK

Publication Release Date: September 2005

Revision A.2

- 16 -

W681360

T_FTRHM

T_MCK

T_RISE

T_FTRSM

T_FALL

MCLK

T_MCKH

T_MCKL

T_BCK

BCLKT

T_FTRS

T_FTRH

T_BCKH

T_FS

T_BCKL

T_FTFS

T_FTFH

FST

T_BDTD

T_HID

PCMT

MSB

LSB

T_BCK

BCLKR

(BCLKT)

T_FRRS

T_FRRH

T_BCKH

T_BCKL

T_FRFS

T_FRFH

FSR

T_DRS

PCMR

T_DRH

MSB

LSB

FIGURE 8.2: SHORT FRAME SYNC PCM TIMING

Publication Release Date: September 2005

Revision A.2

- 17 -

W681360

TABLE 8.2: SHORT FRAME SYNC PCM TIMING PARAMETERS

SYMBOL

1/T_FS

DESCRIPTION

FST, FSR Frequency

MIN

---

TYP

8

MAX

---

UNIT

kHz

1/T_BCK

T_BCKH

T_BCKL

T_FTRH

T_FTRS

T_FTFH

T_FTFS

T_BDTD

T_HID

BCLKT, BCLKR Frequency

BCLKT, BCLKR HIGH Pulse Width

BCLKT, BCLKR LOW Pulse Width

BCLKT Falling Edge to FST Rising Edge Hold Time

FST Rising Edge to BCLKT Falling edge Setup Time

BCLKT Falling Edge to FST Falling Edge Hold Time

FST Falling Edge to BCLKT Falling Edge Setup Time

BCLKT Rising Edge to Valid PCMT Delay Time

Delay Time from BCLKT Falling Edge at last PCMT bit

(LSB) to PCMT Output High Impedance

256

50

20

80

50

10

---

4800

---

60

kHz

ns

T_FRRH

T_FRRS

T_FRFH

T_FRFS

T_DRS

BCLKR Falling Edge to FSR Rising Edge Hold Time

FSR Rising Edge to BCLKR Falling edge Setup Time

BCLKR Falling Edge to FSR Falling Edge Hold Time

FSR Falling Edge to BCLKR Falling Edge Setup Time

Valid PCMR to BCLKR Falling Edge Setup Time

PCMR Hold Time from BCLKR Falling Edge

20

80

50

1

---

ns

T_DRH

50

Publication Release Date: September 2005

Revision A.2

- 18 -

W681360

TABLE 8.3: GENERAL PCM TIMING PARAMETERS

SYMBOL

1/T_MCK

DESCRIPTION

MIN

TYP

256

MAX

---

UNIT

kHz

---

Master Clock Frequency

512

1536

1544

2048

2560

4096

4800

T_MCKH

T_MCK

T_MCKH

/

MCLK Duty Cycle for 256kHz Operation

45%

50

55%

---

Minimum Pulse Width HIGH for

MCLK(512kHz or Higher)

Minimum Pulse Width LOW for MCLK

(512kHz or Higher)

MCLK falling Edge to FST Rising Edge

Hold Time

---

ns

T_MCKL

50

---

T_FTRHM

T_FTRSM

50

---

FST Rising Edge to MCLK Falling edge

Setup Time

50

---

T_RISE

T_FALL

Rise Time for All Digital Signals

Fall Time for All Digital Signals

---

50

ns

Publication Release Date: September 2005

Revision A.2

- 19 -

W681360

9. ABSOLUTE MAXIMUM RATINGS

9.1. ABSOLUTE MAXIMUM RATINGS

Condition

Junction temperature

Value

150⁰C

-65⁰C to +150⁰C

Storage temperature range

Voltage applied to any pin

(V_SS- 0.3V) to (V_DD+ 0.3V)

(V_SS– 1.0V) to (V_DD+ 1.0V)

-0.5V to +6V

Voltage applied to any pin (Input current limited to +/-20 mA)

V_DD- V_SS

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability. Functional operation is not implied at these conditions.

9.2. OPERATING CONDITIONS

Condition

Industrial operating temperature

Value

-40⁰C to +85⁰C

Supply voltage (V_DD)

Ground voltage (V_SS)

+2.7V to +5.25V

0V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely

affect the life and reliability of the device.

Publication Release Date: September 2005

- 20 -

Revision A.2

W681360

10. ELECTRICAL CHARACTERISTICS

10.1. GENERAL PARAMETERS

V_DD=2.7V – 3.6V; V_SS=0V; T_A=-40°C to +85°C;

Symbol Parameters

Conditions

Min ⁽²⁾

Typ

Max

Units

(1)

(2)

V_IL

V_IH

V_OL

V_OH

I_DD

I_SB

I_PD

I_IL

Input LOW Voltage

0.6

V

Input HIGH Voltage

2.2

PCMT Output LOW Voltage

I_OL= 1.6 mA

0.4

4.7

PCMT Output HIGH Voltage

I_OL= -1.6 mA

V_DD–0.5

V

V_DDCurrent (Operating) - ADC + DAC

3.25

mA

No Load

(3)

V_DDCurrent (Standby)

FST&FSR =V_ss; PUI=V_DD

1

100

10

μA

(3)

V_DDCurrent (Power Down)

Input Leakage Current

PUI= V_ss

0.03

V_SS<V_IN<V_DD

-10

+10

V_SS<PCMT<V_DD

High Z State

I_OL

PCMT Output Leakage Current

C_IN

Digital Input Capacitance

PCMT Output Capacitance

10

15

pF

C_OUT

PCMT High Z

1. Typical values: T_A= 25°C , V_DD= 3.0 V

2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all

specifications are 100 percent tested.

3. No DC load from VREF & VAG to Vss

Publication Release Date: September 2005

Revision A.2

- 21 -

W681360

10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS

V_DD=2.7V to 3.6V; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG; 0dBm0 = 0.436 Vrms = -

5dBm @ 600 Ohm; FST =FSR = 8kHz;MCLK=BCLK= 2.048 MHz

PARAMETER

SYM.

CONDITION

TYP.

TRANSMIT

(A/D)

RECEIVE

(D/A)

UNIT

MIN.

MAX.

MIN.

MAX.

Absolute Level

L_ABS

0.616

0.436

3.2

0.886

0

---

V_PK

V_RMS

dBm0

V_PK

0 dBm0 = -5dBm @ 600Ω

Max. Transmit

Level

Absolute Gain (0

dBm0 @ 1020Hz;

T_A=+25°C)

T_XMAX

G_ABS

---

0 dBm0 @ 1020Hz;

T_A=+25°C

-0.20

+0.20 -0.20 +0.20

dB

Absolute Gain

variation with

Temperature

Frequency

Response,

Relative to 0dBm0

@ 1020Hz

G_ABST

0

-0.05

-0.10

+0.05 -0.05 +0.05

+0.10 -0.10 +0.10

dB

T_A=0°C to T_A=+70°C

T_A=-40°C to T_A=+85°C

G_RTV

15Hz

50Hz

---

-1.4

-0.2

-0.7

---

-0.5

-0.2

0

-45

-30

-26

60Hz

0

200Hz

-0.4

+0.2

+0.15

0

(HB=0)

+0.2

+0.25

+0.2

+0.15

0

300 to 1600Hz

1600 to 2400Hz

2400 to 3000Hz

3300Hz

3400Hz

3600Hz

-0.25

-0.4

-0.8

---

0

---

-12.5

-30

4000Hz

4600Hz to 100kHz

-12.5

-32

---

Publication Release Date: September 2005

Revision A.2

- 22 -

W681360

10.3. ANALOG DISTORTION AND NOISE PARAMETERS

V_DD=2.7V to 3.6V; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG; 0dBm0 = 0.436 Vrms = -

5dBm @ 600 Ohm; FST =FSR = 8kHz;MCLK=BCLK= 2.048 MHz

PARAMETER

SYM.

CONDITION

TRANSMIT (A/D)

MIN. TYP. MAX.

RECEIVE (D/A)

MIN. TYP. MAX.

UNIT

Total Distortion

vs. Level Tone

(1020Hz, C-

Message

D_LT

+3 dBm0

0 dBm0

45

50

55

60

54

44

34

24

14

---

50

48

45

60

63

60

55

47

37

27

17

---

dBC

-10 dBm0

-20 dBm0

-30 dBm0

-40 dBm0

-50 dBm0

-60 dBm0

51

50

48

Weighted)

45

35

25

41

32

22

12

14

Spurious Out-Of-

Band at RO-

(300Hz to 3400Hz

@ 0dBm0)

Crosstalk

(1020Hz @

0dBm0)

Absolute Group

Delay

Group Delay

Distortion (relative

to group delay @

1200Hz)

D_SPO

4600Hz to 7600Hz

7600Hz to 8400Hz

8400Hz to 100000Hz

---

-30

-40

-30

dB

D_XT

---

-75

---

-75

1200Hz (HB=0)

360

240

τ_ABS

τ_D

μsec

500Hz

600Hz

1000Hz

2600Hz

2800Hz

C-message weighted

---

750

380

130

750

18

---

750

370

120

750

12

Idle Channel

Noise

N_IDL

dBrnc0

dBm0p

-72

-74

Psophometric weighted

Publication Release Date: September 2005

Revision A.2

- 23 -

W681360

10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS

V_DD=2.7V to 3.6V; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG

;

PARAMETER

AI Input Offset Voltage

AI Input Current

AI Input Resistance

AI Input Capacitance

AI Common Mode Input Voltage

Range

SYM.

V_OFF,AI

I_IN,AI

R_IN,AI

C_IN,AI

CONDITION

AI+, AI-

AI+, AI- to V_AG

AI+, AI-

MIN.

---

10

---

TYP.

---

MAX.

±25

±1.0

---

10

V_DD-1.2

UNIT.

mV

±0.1

---

μA

MΩ

pF

V

V_CM,AI

1.2

---

AI Common Mode Rejection Ratio

AI Amp Gain Bandwidth Product

CMRR_TIAI+, AI-

---

60

---

dB

kHz

GBW_TI

AO, R_LD≥10kΩ

2500

AI Amp DC Open Loop Gain

AI Amp Equivalent Input Noise

AO Output Voltage Range

Load Resistance

Load Capacitance

AO & RO Output Current

RO- Output Resistance

RO- Output Offset Voltage

Analog Ground Voltage

G_TI

N_TI

V_TG

R_LDTGRO

C_LDTGAO

C_LDTGRO

I_OUT1

R_RO-

V_OFF,RO-

V_AG

---

0.4

2

---

±1.0

---

95

-24

---

1

---

V_DD-0.4

---

100

200

---

dB

dBrnC

V

AO, R_LD≥10kΩ

C-Message Weighted

R_LD=2kΩ to V_AG

AO, RO to V_AG

AO

kΩ

pF

RO

mA

0.5 ≤AO,RO-≤ V_DD-0.5

RO-, 0 to 3400Hz

RO- to V_AG

Relative to V_SS(no

load)

---

Ω

mV

V

---

±25

V_DD/2+0.1

V_DD/2-0.1 V_DD/2

V_AGOutput Resistance

R_VAG

---

12.5

Within ±25mV change

Ω

25

Power Supply Rejection Ratio (0 to

100kHz to V_DD, C-message. All

signals referenced to V_AG)

PSRR

Transmit

Receive

40

60

---

dBC

PAI Input Offset Voltage

PAI Input Current

PAI Input Resistance

PAI Amp Gain Bandwidth Product

V_OFF,PAI

I_IN,PAI

R_IN,PAI

GBW_PI

PAI

---

10

---

mV

±25

±1.0

---

±0.05

---

1000

μA

MΩ

kHz

PAI to V_AG

PAO- no load

(@10kHz)

PAO+ to PAO-

---

Output Offset Voltage

Load Capacitance

V_OFF,PO

C_LDPO

---

mV

pF

±50

1000

PAO+, PAO-

differentially or PAO+,

PAO to V_AG

Publication Release Date: September 2005

Revision A.2

- 24 -

W681360

V_DD=2.7V to 3.6V; V_SS=0V; T_A=-40°C to +85°C; all analog signals referred to V_AG

;

PARAMETER

PAO Output Current

SYM.

I_OUTPAO

CONDITION

0.4 ≤ PAO+,PAO--≤

V_DD-0.4

MIN.

±10.0

TYP.

---

MAX.

---

UNIT.

mA

PAO Output Resistance

PAO Differential Gain

R_PAO

G_PAO

PAO+ to PAO-

---

-0.2

1

0

---

+0.2

Ω

dB

R_LD=300Ω, +3dBm0,

1kHz, PAO+ to PAO-

PAO Differential Signal to Distortion

C-Message weighted

D_PAO

45

---

60

40

---

dBC

Z_LD=300Ω

Z_LD=100nF + 20Ω

Z_LD=100Ω (10mA

limit)

PAO Power Supply Rejection Ratio

(0 to 25kHz to V_DD, Differential out)

PSRR_PA0 to 4kHz

40

---

55

40

---

dB

4 to 25kHz

O

Publication Release Date: September 2005

Revision A.2

- 25 -

W681360

10.5. DIGITAL I/O

10.5.1. PCM Codes for Zero and Full Scale

Level

Sign bit

Magnitude Bits

+ Full Scale

0

1111 1111 1111

+ One Step

Zero

- One Step

- Full Scale

0

1

0000 0000 0001

0000 0000 0000

1111 1111 1111

0000 0000 0000

10.5.2. PCM Codes for 1kHz Digital Milliwatt

Phase

Sign bit

Magnitude Bits

0

1

0100 0011 1100

1010 0011 1001

0100 0011 1100

1011 1100 0100

0101 1100 0111

1011 1100 0100

π / 8

3π / 8

5π / 8

7π / 8

9π / 8

11π / 8

13π / 8

15π / 8

Publication Release Date: September 2005

Revision A.2

- 26 -

W681360

11. TYPICAL APPLICATION CIRCUIT

VDD

1.5K

1K

0.1 uF

22 uF

62K

U2

17

18

19

AO

AI-

AI+

+

1.0 uF 3.9K

14

12

13

8 KHz Frame Sy nc

FST

BCLKT

PCMT

100pF

1.0 uF

3.9K

2.048 MHz

Bit Clock

100pF

11

MCLK

ELECTRET

MICROPHONE

20

1

PCM OUT

PCM IN

VAG

VREF

62K

8

9

7

PCMR

BCLKR

FSR

0.01 uF

0.1 uF

2

3

4

5

RO-

PAI

27K

1.5K

16 HP FILTER SELECT

10

PAO-

HB

PUI

POWER CONTROL

PAO+

W681360

SPEAKER

FIGURE 11.1: TYPICAL HANDSET INTERFACE

Publication Release Date: September 2005

Revision A.2

- 27 -

W681360

12. PACKAGE DRAWING AND DIMENSIONS

12.1. 20L SOG (SOP)-300MIL

SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS

c

11

20

E

H

E

L

1

10

O

D

0.2

A

Y

SEATING

e

GAUGE

A

b

DIMENSION (MM)

DIMENSION (INCH)

MAX.

MIN.

MAX.

MIN.

SYMBOL

A

A1

2.35

0.10

2.65

0.30

0.093

0.004

0.104

0.012

b

c

E

D

e

0.33

0.23

7.40

0.51

0.32

7.60

0.013

0.009

0.291

0.496

0.020

0.013

0.299

0.512

12.60

13.00

1.27 BSC

0.050 BSC

H_E

Y

L

10.00

-

0.40

0º

10.65

0.10

1.27

8º

0.394

-

0.016

0º

0.419

0.004

0.050

8º

0

Publication Release Date: September 2005

Revision A.2

- 28 -

W681360

12.2. 20L SSOP-209 MIL

SHRINK SMALL OUTLINE PACKAGE DIMENSIONS

D

11

20

DTEAIL

H

E

1

10

b

A

SEATING PLANE

θ

L

Y

L

e

b

A

DETAIL

DIMENSION (MM)

DIMENSION (INCH)

NOM.

MAX.

MIN.

NOM.

MAX.

MIN.

SYMBOL

A

A1

A2

b

c

D

E

H_E

e

L

L1

Y

-

2.00

-

0.079

-

0.05

1.65

0.22

0.09

6.90

5.00

7.40

-

0.002

0.065

0.009

0.004

0.272

0.197

0.291

-

0.021

-

0

-

0.069

-

1.75

-

7.20

5.30

7.80

0.65

0.75

1.25

-

1.85

0.38

0.25

7.50

5.60

8.20

-

0.95

-

0.10

8º

-

0.015

0.010

0.295

0.220

0.323

-

0.037

-

0.004

8º

-

0.283

0.209

0.307

0.0256

0.030

0.050

-

0.55

-

0

0º

-

Publication Release Date: September 2005

Revision A.2

- 29 -

W681360

12.3. 20L TSSOP - 4.4X6.5MM

PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS

DIMENSION (MM)

DIMENSION (INCH)

SYMBOL

MIN.

-

NOM.

MAX.

1.20

0.15

MIN.

-

NOM.

MAX.

A

A1

A2

E

-

0.047

0.006

0.041

0.177

0.05

0.002

0.031

0.169

0.80

4.30

0.90

1.05

4.50

0.035

0.173

4.40

HE

D

6.40 BSC

.252 BSC

0.256

6.40

0.50

6.50

6.60

0.75

0.252

0.020

0.260

0.030

L

0.60

0.024

L1

b

1.00 REF

0.039 REF

-

0.19

-

0.30

0.007

0.012

e

0.65 BSC

0.026 BSC

-

c

0

0.09

0º

-

0.20

8º

0.004

0º

0.008

8º

-

Y

0.10 BASIC

0.004 BASIC

Publication Release Date: September 2005

Revision A.2

- 30 -

W681360

12.3. QFN-32L

QUAD FLAT PACK NO LEADS PACKAGE (QFN) DIMENSIONS

L

Publication Release Date: September 2005

Revision A.2

- 31 -

W681360

13. ORDERING INFORMATION

Winbond Part Number Description

W681360_ _

Product Family

W681360

Package Material:

Blank

=

Standard Package

G

Pb-free (RoHS) Package

Package Type:

S

=

20-Lead Plastic Small Outline Package (SOG/SOP)

R

W

Y

20-Lead Plastic Shrink Small Outline Package (SSOP)

20-Lead Plastic Thin Shrink Small Outline Package (TSSOP)

32-Quad Flat No leads Package (QFN)

When ordering W681360 series devices, please refer to the following part numbers.

Part Number

W681360S

W681360R

W681360W

W681360SG

W681360RG

W681360WG

W681360YG*

* W681360YG available in Pb-free (RoHS) package only

Publication Release Date: September 2005

Revision A.2

- 32 -

W681360

14. VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A.1

A.15

April 2004

April 2005

All

32

Preliminary Specification

Add Important Note

A.16

September,

2005

2

Added reference to Pb-free RoHS packaging and to V_RMS

Added reference to QFN-32L package

6, 7

9

Added QFN-32L Pinout

Added Pin numbers to Tables

10, 12 Capitalized logic HIGH/LOW

22

27

31

32

Added Reference to V_RMS

Improved Application Diagram

Added QFN-32L Mechanical Dimensions

Added Y and G package ordering code

Publication Release Date: September 2005

Revision A.2

- 33 -

W681360

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control instruments,

airplane or spaceship instruments, transportation instruments, traffic signal instruments,

combustion control instruments, or for other applications intended to support or sustain life.

Further more, Winbond products are not intended for applications wherein failure of Winbond

products could result or lead to a situation wherein personal injury, death or severe property

or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

The information contained in this datasheet may be subject to change

without notice. It is the responsibility of the customer to check the

Winbond USA website (www.winbond-usa.com) periodically for the latest

version of this document, and any Errata Sheets that may be generated

Publication Release Date: September 2005

- 34 -

Revision A.2

型号:	W681360RG
是否Rohs认证：	符合
生命周期：	Transferred
零件包装代码：	SSOP
包装说明：	SSOP, SSOP20,.3
针数：	20
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.28
压伸定律：	MU-LAW
滤波器：	YES
最大增益公差：	0.2 dB
JESD-30 代码：	R-PDSO-G20
长度：	7.2 mm
线性编码：	13-BIT
湿度敏感等级：	3
功能数量：	1
端子数量：	20
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP20,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
座面最大高度：	2 mm
子类别：	Codecs
最大压摆率：	0.0047 mA
标称供电电压：	3 V
表面贴装：	YES
电信集成电路类型：	LINEAR CODEC
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	5.3 mm
Base Number Matches：	1

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