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W83194BR-703/W83194BG-703

STEPLESS CLOCK FOR SIS 741 CHIPSET

W83194BR-703/W83194BG-703

WINBOND CLOCK GENERATOR

FOR SIS 741/964 CHIPSETS

Date: Jan./23/2006

Revision: 0.8

W83194BR-703/W83194BG-703

Data Sheet Revision History

PAGES

DATES

VERSION

WEB VERSION

MAIN CONTENTS

All of the versions before 0.50 are

for internal use.

1

2

n.a.

09/03/2003

11/12/2003

0.5

0.6

n.a.

First published preliminary version.

2,3,5,

6~14,

16~19

Delete some power manage pin,

Add register, SRC fix 100MHz, Add

AC/DC

3

4

2,3,6,8,

18

Correct IC version and default

value

04/18/2004

01/23/2006

0.7

0.8

n.a.

5

6

Add lead free part W83194BG-703

7

8

9

10

Please note that all data and specifications are subject to change without notice. All

the trademarks of products and companies mentioned in this data sheet belong to

their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or

systems where malfunction of these products can reasonably be expected to result

in personal injury. Winbond customers using or selling these products for use in such

applications do so at their own risk and agree to fully indemnify Winbond for any

damages resulting from such improper use or sales.

Publication Release Date: Jan. 2006

- I -

Revision 0.8

W83194BR-703/W83194BG-703

Table of Content-

1.

2.

3.

4.

5.

GENERAL DESCRIPTION ......................................................................................................... 1

PRODUCT FEATURES .............................................................................................................. 1

PIN CONFIGURATION............................................................................................................... 2

BLOCK DIAGRAM ...................................................................................................................... 3

PIN DESCRIPTION..................................................................................................................... 4

5.1

5.2

5.3

5.4

5.5

5.6

Crystal I/O.................................................................................................................................4

CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs ...............................................................4

Fixed Frequency Outputs.........................................................................................................5

I2C Control Interface ................................................................................................................5

Power Management Pins.........................................................................................................5

Power Pins................................................................................................................................6

6.

7.

FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7

I²C CONTROL AND STATUS REGISTERS............................................................................... 8

7.1

Register 0: Frequency Select (Default = 20h).........................................................................8

Register 1: CPU Control (1 = Enable, 0 = Stopped) (Default: ECh).......................................8

Register 2: PCI, ZCLK Control (1 = Enable, 0 = Stopped) (Default: FFh) .............................9

Register 3: PCI, AGP Control (1 = Enable, 0 = Stopped) (Default: FFh)...............................9

Register 4: 48MHz, REF, SRC Control (1 = Enable, 0 = Stopped) (Default: FFh)................9

Register 5: Watchdog Control (Default: 04h) ........................................................................10

Register 6: Skew Control (Default: 25h)................................................................................10

Register 7: Winbond Chip ID (Default: 77h) (Read only)......................................................11

Register 8: M/N (Default: 90h) ...............................................................................................11

Register 9: N (Default: BBh)...................................................................................................11

Register 10: N & N3 (Default: 3Bh)........................................................................................12

Register 11: Spread Spectrum Programming (Default: 0Eh) ...............................................12

Register 12: Divisor and Step-less Enable Control (Default: 89h) .......................................12

Register 13: M/N Control (Default: 0Ah)................................................................................13

Register 14: Spread Spectrum Control (Default: 10h)..........................................................14

Register 15: Spread Spectrum type Control (Default: 2Ch) .................................................14

Register 16: Skew Control (Default: 24h)..............................................................................15

Register 17: Slew rate Control (Default: 00h)........................................................................15

Register 18: Slew rate Control (Default: 00h)........................................................................15

Register 19: Slew rate Control (Default: D2h).......................................................................16

Register 20: SRC select Control (Default: 88h) ....................................................................16

Register 21: Fix Mode Control (Default: 00h)........................................................................17

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.20

7.21

7.22

-II-

W83194BR-703/W83194BG-703

8.

9.

ACCESS INTERFACE.............................................................................................................. 18

8.1

8.2

8.3

8.4

Block Write protocol ...............................................................................................................18

Block Read protocol...............................................................................................................18

Byte Write protocol.................................................................................................................18

Byte Read protocol.................................................................................................................18

SPECIFICATIONS .................................................................................................................... 19

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

ABSOLUTE MAXIMUM RATINGS .......................................................................................19

General Operating Characteristics ........................................................................................19

Skew Group timing clock........................................................................................................19

CPU (Open Drain) Electrical Characteristics.........................................................................20

SRC 0.7V Electrical Characteristics ......................................................................................20

AGP, ZCLK Electrical Characteristics ...................................................................................20

PCI Electrical Characteristics.................................................................................................21

24M, 48M Electrical Characteristics ......................................................................................21

REF Electrical Characteristics ...............................................................................................21

IOAPIC Electrical Characteristics ..........................................................................................22

10.

11.

12.

ORDERING INFORMATION..................................................................................................... 22

HOW TO READ THE TOP MARKING...................................................................................... 23

PACKAGE DRAWING AND DIMENSIONS.............................................................................. 24

Publication Release Date: Jan. 2006

- III -

Revision 0.8

W83194BR-703/W83194BG-703

1. GENERAL DESCRIPTION

The W83194BR-703 is a Clock Synthesizer for SIS 741 chipset with 964 South Bridge. W83194BR-

703 provides all clocks required for high-speed microprocessor and provides step-less frequency

programming and 32 different frequencies of CPU, PCI, and AGP clocks setting, support two ZCLK

clock and one pair current mode differential SRC clock outputs; all clocks are externally selectable

with smooth transitions.

The W83194BR-703 provides I²C serial bus interface to program the registers to enable or disable

each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable

S.S.T. scale to reduce EMI.

The W83194BR-703 also has watchdog timer to support auto-reset when systems hanging caused by

improper frequency setting.

The W83194BR-703 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

2. PRODUCT FEATURES

• 1 3.3V open drain Differential pairs clock outputs for CPU

• 1 3.3V open drain singled-ended clock output for chipset host bus.

• 1 pair 3.3V current mode differential SRC clock.

• 2 3.3V ZCLK clock outputs

• 2 AGP clock outputs

• 8 PCI synchronous clocks

• 2 2.5V IOAPIC clock outputs

• 1 24_48Mhz clock output for super I/O.

• 1 12_48 MHz clock output for USB.

• 3 14.318MHz REF clock outputs.

• ZCLK/AGP/PCI clock out supports synchronous and asynchronous mode

• Smooth frequency switch with selections from 100 to 218MHz

• Step-less frequency programming

• I²C 2-Wire serial interface and support byte read/write and block read/write.

• -0.5% and +/- 0.25% center type spread spectrum

• Programmable S.S.T. scale to reduce EMI

• Programmable registers to enable/stop each output and select modes

• Programmable clock outputs Skew control

• 48-pin SSOP package

Publication Release Date: Jan. 2006

- 1 -

Revision 0.8

W83194BR-703/W83194BG-703

3. PIN CONFIGURATION

#: Active low

*: Internal pull up resistor 120K to VDD

&: Internal Pull-down resistor 120K to GND

-2-

W83194BR-703/W83194BG-703

4. BLOCK DIAGRAM

12_48MHz

PLL2

Divider

24_48MHz^

3

XTAL

OSC

XIN

XOUT

REF 0:2

2

CPUT0:1

PLL1

CPUC0

Spread

Spectrum

VCOCLK

SRCT

SRCC

2

ZCLK0:1

M/N/Ratio

ROM

2

IOAPIC0:1

AGP 0:1

Divider

2

8

FS(0:3)

SEL12_48MHz#^&

SEL24_48MHz#^&

Latch

&POR

PCI_F0:1,

PCI_0:5

Control

Logic

&Config

Register

Rref

SDATA*

SCLK*

I2C

Interface

Publication Release Date: Jan. 2006

Revision 0.8

- 3 -

W83194BR-703/W83194BG-703

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

DESCRIPTION

IN

IN_tp120k

IN_td120k

OUT

OD

#

Input

Latched input at power up, internal 120kΩ pull up.

Latched input at power up, internal 120kΩ pull down.

Output

Open Drain

Active Low

*

Internal 120kΩ pull-up

Internal 120 kΩ pull-down

&

5.1 Crystal I/O

PIN NAME

TYPE

DESCRIPTION

Crystal input with internal loading capacitors (18pF) and

feedback resistors.

Crystal output at 14.318MHz nominally with internal loading

capacitors (18pF).

6

XIN

XOUT

IN

7

OUT

5.2 CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs

PIN NAME

TYPE

DESCRIPTION

CPUT0

38,37

OD 3.3V open drain differential clock outputs for AMD K7 CPU

CPUC0

CPUT1

3.3V open drain singled –ended synchronize with CPUT0,

40

OD

For chipset host bus

43,42

31,30

9,10

SRCT, SRCC

AGP_0: 1

ZCLK0: 1

PCI_F0

OUT Current mode differential clock outputs for SRC

OUT 3.3V AGP clock outputs.

OUT 3.3V ZCLK clock outputs, For MuTIOL bus.

OUT 3.3V PCI free running clock output.

14

Latched input for FS2 at initial power up for H/W selecting

IN_tp120k

FS2*

the output frequency. This is internal 120K pull up.

PCI_F1

FS3*

OUT 3.3V PCI free running clock output.

15

Latched input for FS3 at initial power up for H/W selecting

IN_tp120k

the output frequency, This is internal 120K pull up.

16,17,20,21

,22,23

PCI [0:5]

OUT Low skew (< 250ps) PCI clock outputs.

OUT 2.5V IOAPIC outputs.

47,46

IOAPIC [0:1]

-4-

W83194BR-703/W83194BG-703

5.3 Fixed Frequency Outputs

PIN NAME

REF0

TYPE

DESCRIPTION

OUT

14.318MHz output.

2

Latched input for FS0 at initial power up for H/W selecting

the output frequency. This is internal 120K pull down.

FS0^&

IN_td120k

REF1

FS1^&

OUT

14.318MHz output.

3

4

Latched input for FS1 at initial power up for H/W selecting

the output frequency. This is internal 120K pull down.

14.318MHz output.

IN_td120k

REF2

12_48MHz

OUT

12 MHz (default) or 48MHz clock output.

Latched input at initial power up for 12_48MHz output type

selecting, SEL12_48MHz= 0 is 48 MHz, SEL12_48MHz=1

is 12MHZ; This is internal 120KΩ pull up.

27

26

SEL12_48MHz#

*

IN_tp120k

OUT

24_48MHz

24MHz or 48MHz (default) clock output.

Latched input at initial power up for 24_48MHz output type

selecting, SEL24_48MHz= 0 is 48 MHz, SEL24_48MHz=1

is 24MHZ; This is internal 120KΩ pull down.

SEL24_48#^&

IN_td120k

5.4 I2C Control Interface

PIN NAME

SDATA*

TYPE

DESCRIPTION

Serial data of I²C 2-wire control interface with internal pull-

up resistor.

33

I/OD

Serial clock of I²C 2-wire control interface with internal pull-

up resistor.

12

SCLK*

IN

5.5 Power Management Pins

PIN NAME

TYPE

DESCRIPTION

Deciding the reference current for the SRCT/C pairs. The

pin was connected to the precision resistor tied to ground to

decide the appropriate current. The table is show as follows.

MULTSEL Board Target Reference R, Output Ioh @

(PIN 11) Trace/ Term Iref=VDD/(3*Rr Current

Z

)

34

IREF

OUT

1

0

50 Ohms

Ioh=

6*Iref

0.7V

@ 50

R=475 1%

Iref=2.32mA

R=221 1%

Iref=5mA

50 Ohms

Ioh=

4*Iref

1.0V

@ 50

Publication Release Date: Jan. 2006

Revision 0.8

- 5 -

W83194BR-703/W83194BG-703

5.6 Power Pins

PIN NAME

TYPE

DESCRIPTION

1

VDDREF

VDDPCI

VDDAGP

VDDSRC

VDD48

VDDZ

PWR 3.3V power supply for REF.

PWR 3.3V power supply for PCI.

PWR 3.3V power supply for AGP.

PWR 2.5V power supply for SRC.

PWR 3.3V power supply for 48MHz.

PWR 3.3V power supply for ZCLK.

PWR 2.5V power supply for IOAPIC

PWR 3.3V power supply for Analog core logic.

13,19

29

44

28

11

48

36

VDDI

VDDA

5,8,18,24,25,32,

35,39,41,45

GND

PWR Ground pin

-6-

W83194BR-703/W83194BG-703

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL

[4:0] (Register 0 bit 7 ~ 3).

FS4

0

1

FS3 FS2 FS1 FS0 CPU (MHZ) SRC (MHZ) ZCLK (MHZ) AGP (MHZ)

PCI (MHZ)

33.33

33.50

31.67

33.33

33.66

31.67

33.33

34.72

33.66

31.67

33.33

33.50

31.67

34.33

35.00

35.67

36.33

34.33

35.00

35.67

36.33

34.33

35.00

35.67

36.33

34.33

35.00

35.67

36.33

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

200.00

200.99

190.00

100.00

100.99

95.00

100.00

133.33

133.99

126.67

133.33

134.65

126.67

133.33

138.88

134.65

126.67

133.33

133.99

126.66

137.33

140.00

142.67

145.33

137.33

140.00

142.67

145.33

137.33

140.00

142.67

145.33

137.33

140.00

142.67

145.33

66.67

67.00

63.33

66.67

67.33

63.33

66.67

69.44

67.33

63.33

66.67

67.00

63.33

68.67

70.00

71.33

72.67

68.67

70.00

71.33

72.67

68.67

70.00

71.33

72.67

68.67

70.00

71.34

72.67

160.00

166.66

161.58

152.00

133.33

133.99

126.66

206.00

210.00

214.00

218.00

103.00

105.00

107.00

109.00

164.80

168.00

171.20

174.40

137.33

140.00

142.67

145.33

Publication Release Date: Jan. 2006

Revision 0.8

- 7 -

W83194BR-703/W83194BG-703

7. I²C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select (Default = 20h)

BIT

7

NAME

SSEL [4]

PWD

DESCRIPTION

0

1

0

Frequency selection by software via I²C

6

SSEL [3]

SSEL [2]

SSEL [1]

SSEL [0]

5

4

3

Enable software table selection FS [4:0].

0 = Hardware table setting (Jump mode).

1 = Software table setting through Bit7~3. (Jump less mode)

Enable spread spectrum mode under clock output.

0 = Spread Spectrum mode disable

2

1

EN_SSEL

EN_SPSP

0

1 = Spread Spectrum mode enable

After watchdog timeout

0 = Reload the hardware FS [4:0] latched pins setting.

0

EN_SAFE_FREQ

0

1 = Reload the desirable frequency table selection defined at Reg-5

Bit 4~0.

7.2 Register 1: CPU Control (1 = Enable, 0 = Stopped) (Default: ECh)

BIT

PIN NO

PWD

DESCRIPTION

7

Reserved

1

Reserved

6

40

1

CPUT1 output control

CPUT0 / C0 output control

5

38,37

1

4

Reserved

X

Reserved. Default: 0 (Read only)

3

15

14

3

X

Power on latched value of FS3 pin. Default: 1 (Read only)

Power on latched value of FS2 pin. Default: 1 (Read only)

Power on latched value of FS1 pin. Default: 0 (Read only)

Power on latched value of FS0 pin. Default: 0 (Read only)

2

X

1

X

0

2

X

-8-

W83194BR-703/W83194BG-703

7.3 Register 2: PCI, ZCLK Control (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

7

PIN NO

-

PWD

DESCRIPTION

1

Reserved

6

15

14

10

9

PCI_F1 output control

PCI_F0 output control

ZCLK1 output control

ZCLK0 output control

PCI5 output control

PCI4 output control

PCI3 output control

5

4

3

2

23

22

21

1

0

7.4 Register 3: PCI, AGP Control (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

7

PIN NO

20

PWD

DESCRIPTION

1

PCI2 output control

PCI1 output control

PCI0 output control

6

17

5

16

12 _ 48 MHz output selection, 1: 12 MHz (default) 0: 48 MHz.

Default value follow hardware trapping data on SEL12_48# pin.

IOAPIC1 output control

4

SEL12_48

X

3

2

1

0

47

46

30

31

1

IOAPIC0 output control

AGP_1 output control

AGP_0 output control

7.5 Register 4: 48MHz, REF, SRC Control (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

PIN NO

PWD

DESCRIPTION

7

26

1

24_48MHz output control

12_48MHz output control

Reserved

6

27

5

-

4

REF2 output control

REF1 output control

REF0 output control

SRC output control

Reserved

3

2

47,46

-

1

0

Publication Release Date: Jan. 2006

Revision 0.8

- 9 -

W83194BR-703/W83194BG-703

7.6 Register 5: Watchdog Control (Default: 04h)

BIT

NAME

PWD

DESCRIPTION

24 / 48 MHz output selection, 1: 24 MHz 0: 48 MHz (Default), Default

value follow hardware trapping data on SEL24_48# pin.

7

SEL24_48

X

Program this bit =>

1: Enable Watchdog Timer feature.

0: Disable Watchdog Timer feature.

Read-back this bit =>

6

CNT_EN

0

During timer count down the bit read back to 1.

If count to zero, this bit read back to 0.

Read Back only. Timeout Flag. This bit is Read Only.

1: Watchdog has ever started and counts to zero.

0: Watchdog is restarted and counting.

5

WD_TIMEOUT

0

4

3

2

1

0

SAF_FREQ [4]

SAF_FREQ [3]

SAF_FREQ [2]

SAF_FREQ [1]

SAF_FREQ [0]

0

1

0

These bits will be reloaded in Reg-0 to select frequency table. As the

watchdog is timeout and EN_SAFE_FREQ=1.

7.7 Register 6: Skew Control (Default: 25h)

BIT

7

NAME

Reserved

CSKEW<2>

CSKEW<1>

CSKEW<0>

PWD

DESCRIPTION

0

1

0

1

0

1

Reserved

6

5

Reserved

4

3

2

CPU1 to CPU0 skew control

Skew resolution is 250ps

1

The decision of skew direction is same as CSKEW<2:0> setting

0

-10-

W83194BR-703/W83194BG-703

7.8 Register 7: Winbond Chip ID (Default: 77h) (Read only)

BIT

7

NAME

PWD

DESCRIPTION

Winbond Chip ID. W83194BR-703 (SA5877).

Winbond Chip ID.

CHPI_ID [7]

CHPI_ID [6]

CHPI_ID [5]

CHPI_ID [4]

CHPI_ID [3]

CHPI_ID [2]

CHPI_ID [1]

CHPI_ID [0]

0

1

0

1

6

5

Winbond Chip ID.

4

Winbond Chip ID.

3

Winbond Chip ID.

2

Winbond Chip ID.

1

Winbond Chip ID.

0

Winbond Chip ID.

7.9 Register 8: M/N (Default: 90h)

BIT

7

NAME

PWD

X

DESCRIPTION

NVAL<8>

MVAL<6>

MVAL<5>

MVAL<4>

MVAL<3>

MVAL<2>

MVAL<1>

MVAL<0>

Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.

6

X

5

X

4

X

Programmable M divisor

3

X

2

X

1

X

0

X

7.10 Register 9: N (Default: BBh)

BIT

7

NAME

NVAL<7>

PWD

X

DESCRIPTION

6

NVAL<6>

NVAL<5>

NVAL<4>

NVAL<3>

NVAL<2>

NVAL<1>

NVAL<0>

X

5

X

4

X

Programmable N divisor bit 7 ~0. The bit 8 is defined in Register 8,

The bit 9 is defined in Register 10

3

X

2

X

1

X

0

X

Publication Release Date: Jan. 2006

- 11 -

Revision 0.8

W83194BR-703/W83194BG-703

7.11 Register 10: N & N3 (Default: 3Bh)

BIT

7

NAME

PWD

X

DESCRIPTION

NVAL<9>

N3VAL<6>

N3VAL<5>

N3VAL<4>

N3VAL<3>

N3VAL<2>

N3VAL<1>

N3VAL<0>

Programmable N divisor bit 9.

6

X

5

X

Programmable N3 divisor bit 6 ~0 for programmable

SRC clock.

4

X

3

X

PS: Frequency range: 86.8M ~ 115.2M

Resolution: 224K

2

X

1

X

0

X

7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)

BIT

7

NAME

SP_UP [3]

PWD

DESCRIPTION

0

1

0

6

SP_UP [2]

Spread Spectrum Up Counter bit 3 ~ bit 0.

5

SP_UP [1]

4

SP_UP [0]

3

SP_DOWN [3]

SP_DOWN [2]

SP_DOWN [1]

SP_DOWN [0]

Spread Spectrum Down Counter bit 3 ~ bit 0

2’s complement representation.

2

1

Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000

0

7.13 Register 12: Divisor and Step-less Enable Control (Default: 89h)

BIT

NAME

PWD

DESCRIPTION

Enable variable accumulation period for M divisor

1: Enable, 0: Disable (Original timing)

7

M_NACC_EN

1

6

5

4

3

2

1

0

KVAL<9>

KVAL<5>

Reserved

KVAL<2>

KVAL<1>

KVAL<0>

X

Define the ZCLK divider ratio

Table-2 integrate the all divider configuration

Reserved

Define the CPU divider ratio

Refer to Table-2

-12-

W83194BR-703/W83194BG-703

Table-2 CPU, ZCLK divider ratio selection Table

ZCLK

BIT5

CPU

LSB

BIT1, 0

MSB

0

1

00

01

10

11

Bit2/

Bit4/

Bit9

0

Div3

Div4

Div2

Div3

Div4

Div5

1

Div5

Div6

Div8

7.14 Register 13: M/N Control (Default: 0Ah)

BIT

NAME

PWD

DESCRIPTION

0: Output frequency depend on frequency table

1: Program all clock frequency by changing M/N value

The equation is

VCO =14.318MHz*(N+4)/ M.

7

EN_MN_PROG

0

Once the watchdog timer timeout, the bit will be clear. Then

the frequency will be decided by hardware default FS<4:0>

or desired frequency select SAF_FREQ [4:0] depend on

EN_SAFE_FREQ (Reg0 - bit 7).

6

5

NVAL<10>

DIVM_P1

X

0

Programmable N divisor bit 10.

Variable accumulation period for M divisor. Depend

On VCO Frequency.

00: 400M

10: 667M

01: 533M

11: 800M

4

DIVM_P0

0

3

2

1

0

IVAL<3>

IVAL<2>

IVAL<1>

IVAL<0>

X

Charge pump current selection

Publication Release Date: Jan. 2006

Revision 0.8

- 13 -

W83194BR-703/W83194BG-703

7.15 Register 14: Spread Spectrum Control (Default: 10h)

BIT

NAME

PWD

DESCRIPTION

CPUT output state in during POWER DOWN or Stop mode assertion.

1: Driven (2*Iref)

0: Tristate (Floating)

7

CPUT_DRI

0

CPUC always tri-state (floating) in power down Assertion.

SRC_T output state in during POWER DOWN or Stop mode assertion.

1: Driven (6*Iref => STOP mode)

6

SRCT_DRI

0

(2*Iref => POWER DOWN)

0: Tristate (Floating)

SRC_C always tri-state (floating) in power down Assertion.

5

4

3

2

1

0

SPCNT<5>

SPCNT<4>

SPCNT<3>

SPCNT<2>

SPCNT<1>

SPCNT<0>

0

1

0

Spread Spectrum Programmable time, the resolution is 280ns. Default

period is 11.8us

7.16 Register 15: Spread Spectrum type Control (Default: 2Ch)

BIT

7

NAME

INV_CPU

PWD

DESCRIPTION

Invert the CPU phase, 0: Default, 1: Inverse

Invert the ZCLK phase, 0: Default, 1: Inverse

Reserved

0

1

0

6

INV_ZCLK

Reserved

SPSP1

5

4

Spread Spectrum type select.

00: Down

1%

01: Down 0.5%

3

SPSP0

1

10: Center +/- 0.5%

11: Center +/- 0.25%

2

1

0

ASKEW<2>

ASKEW<1>

ASKEW<0>

1

0

CPU1 to AGP skew control.

Skew resolution is 250ps

The decision of skew direction is same as ASKEW<2:0> setting

-14-

W83194BR-703/W83194BG-703

7.17 Register 16: Skew Control (Default: 24h)

Bit

7

Name

PWD Description

INV_AGP

INV_PCI

0

1

0

1

0

Invert the AGP phase, 0: Default, 1: Inverse

6

Invert the PCI phase, 0: Default, 1: Inverse

CPU1 to ZCLK skew control

5

ZSKEW<2>

ZSKEW<1>

ZSKEW<0>

PSKEW<2>

PSKEW<1>

PSKEW<0>

Skew resolution is 250ps

4

The decision of skew direction is same as ZSKEW<2:0> setting

3

2

CPU1 to PCI skew control

Skew resolution is 250ps

1

The decision of skew direction is same as PSKEW<2:0> setting

0

7.18 Register 17: Slew rate Control (Default: 00h)

BIT

NAME

PWD

DESCRIPTION

7

Reserved

0

Reserved

Invert the USB12_48 phase, 0: In phase with USB24_48

1: 180 degrees out of phase

6

INV_USB12

0

5

4

3

2

1

0

PCI_F0_S2

PCI_F0_S1

IOAPIC_S2

IOAPIC_S1

AGP_10_S2

AGP_10_S1

0

PCI_F1 / PCI_F0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

IOAPIC1, 0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

AGP_1 / AGP_0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

7.19 Register 18: Slew rate Control (Default: 00h)

BIT

7

NAME

PCI_5_S2

PCI_5_S1

PCI_42_S2

PCI_42_S1

PCI_10_S2

PCI_10_S1

REF_S2

PWD

DESCRIPTION

0

PCI5 slew rate control

11: Strong, 00: Weak, 10/01: Normal

PCI4, 3,2 slew rate control

6

5

11: Strong, 00: Weak, 10/01: Normal

PCI1, 0 slew rate control

4

3

11: Strong, 00: Weak, 10/01: Normal

2

1

REF0, 1, 2 slew rate control

11: Strong, 00: Weak, 10/01: Normal

0

REF_S1

Publication Release Date: Jan. 2006

Revision 0.8

- 15 -

W83194BR-703/W83194BG-703

7.20 Register 19: Slew rate Control (Default: D2h)

BIT

7

NAME

CPU1S_EN

CPU0S_EN

ZCLK_S2

ZCLK_S1

PWD

DESCRIPTION

Stop CPU1 clocks, 1: Enable stop feature, 0: Disable

Stop CPU0 clocks, 1: Enable stop feature, 0: Disable

ZCLK1, 0 slew rate control

1

0

1

6

5

11: Strong, 00: Weak, 10/01: Normal

Invert the USB48 phase

4

3

INV_USB48

0

0: In phase with USB24_48

1: 180 degrees out of phase

2

1

0

USB48_S2

USB48_S1

Reserved

0

1

0

USB48/USB12_48/USB24_48 slew rate control

11: Strong, 00: Weak, 10/01: Normal

Reserved

7.21 Register 20: SRC select Control (Default: 88h)

BIT

7

NAME

Reserved

SEC<6>

SEC<5>

SEC<4>

SEC<3>

SEC<2>

SEC<1>

SEC<0>

PWD

DESCRIPTION

1

0

1

0

Reserved for test only please don’t modify it.

6

5

4

Setting the down count depth. One bit resolution Represent 250ms.

Default time depth is 8*250ms = 2.0 second. If the watchdog timer is

counting, this register will return present down count value.

3

2

1

0

-16-

W83194BR-703/W83194BG-703

7.22 Register 21: Fix Mode Control (Default: 00h)

BIT

NAME

TRI-EN

PWD

DESCRIPTION

7

0

Tri-state all output if set 1

ZCLK output frequency select mode

(Only valid under FIX_ADDR<2:0> is nonzero)

0: Output frequency according to frequency selection table

1: Output frequency according to FIX frequency table

PCI output frequency select mode

6

5

4

FIX_ZCLK

FIX_PCI

0

(Only valid under FIX_ADDR<2:0> is nonzero)

0: Output frequency according to frequency selection table

1: Output frequency according to FIX frequency table

AGP output frequency select mode

(Only valid under FIX_ADDR<2:0> is nonzero)

0: Output frequency according to frequency selection table

1: Output frequency according to FIX frequency table

Reserved for test only please don’t modify it.

FIX_AGP

3

2

1

Reserved

0

FIX_ADDR<2>

FIX_ADDR<1>

Asynchronous ZCLK/AGP/PCI frequency table selection

FIX_ADDR<2:0>

001: 132 / 66 / 33M

011: 132 / 88 / 44M

101: 132 / 66 / 33M

111: 132 / 88 / 33M

010:132 / 75.43 / 37.7M

100:176 / 88 / 44M

0

FIX_ADDR<0>

0

110:132 / 75.43 / 33M

000: Clock from PLL1

Publication Release Date: Jan. 2006

Revision 0.8

- 17 -

W83194BR-703/W83194BG-703

8. ACCESS INTERFACE

The W83194BR-703 provides I²C Serial Bus for microprocessor to read/write internal registers. In the

W83194BR-703 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I²C

address is defined at 0xD2.

Block Read and Block Write Protocol

8.1 Block Write protocol

8.2 Block Read protocol

## In block mode, the command code must filled 8’h00

8.3 Byte Write protocol

8.4 Byte Read protocol

-18-

W83194BR-703/W83194BG-703

9. SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.

Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

PARAMETER

RATING

Absolute 3.3V Core Supply Voltage

Absolute 3.3V I/O Supple Voltage

Operating 3.3V Core Supply Voltage

Operating 3.3V I/O Supple Voltage

Storage Temperature

-0.5V to +4.6V

- 0.5 V to + 4.6 V

3.135V to 3.465V

- 65°C to + 150°C

- 55°C to + 125°C

0°C to + 70°C

Ambient Temperature

Operating Temperature

Input ESD protection (Human body model)

2000V

9.2 General Operating Characteristics

VDD48=VDDAGP=VDDREF=VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

PARAMETER

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

SYMBOL

V_IL

MIN

2.0

2.4

MAX UNITS

TEST CONDITIONS

0.8

V_dc

V_IH

V_OL

0.4

All outputs using 3.3V power

CPU = 100 to 200 MHz

V_OH

Operating Supply Current

I_dd

350

mA

PCI = 33.3 Mhz with load

Input pin capacitance

Output pin capacitance

Input pin inductance

Cin

Cout

Lin

5

6

7

pF

nH

9.3 Skew Group timing clock

VDD48=VDDAGP=VDDREF=VDDPCI = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

PARAMETER

AGP to PCI Skew

CPU to CPU Skew

AGP to AGP Skew

PCI to PCI Skew

MIN

TYP

MAX

3.5

UNITS

ns

TEST CONDITIONS

Measured at 1.5V

1.5

2.6

200

250

500

1000

500

ps

Crossing point

ps

Measured at 1.5V

ps

48MHz to 48MHz Skew

REF to REF Skew

ps

Publication Release Date: Jan. 2006

Revision 0.8

- 19 -

W83194BR-703/W83194BG-703

9.4 CPU (Open Drain) Electrical Characteristics

TA = 0°C to +70°C, external 1.5V pull-up

Parameter

Rise Time

Min

Max

900

Units

ps

Test Conditions

-

100 to 200 Mhz, Vol=20%, Voh=80%

100 to 200Mhz, Vol=20%, Voh=80%

Fall Time

ps

Absolute crossing point

Voltages

550

1250

mV

100 to 200Mhz

Cycle to Cycle jitter

Duty Cycle

250

55

ps

%

100 to 200Mhz

45

9.5 SRC 0.7V Electrical Characteristics

VDDSRC= 3.3V ± 5 %, TA = 0°C to +70°C,

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

100 Mhz , Measure from Vol=0.175 to

Voh=0.525

Rise Time

175

700

ps

100 Mhz, Measure from Vol=0.175 to

Voh=0.525

Fall Time

175

250

700

550

125

55

ps

mV

ps

Absolute crossing point

Voltages

100 Mhz

100 Mhz, Measure from differential

wavefrom

Cycle to Cycle jitter

Duty Cycle

100 Mhz, Measure from differential

wavefrom

45

%

9.6 AGP, ZCLK Electrical Characteristics

VDDAGP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

MIN

500

MAX

2000

250

UNITS

ps

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

Fall Time

ps

Cycle to Cycle jitter

Duty Cycle

ps

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

-20-

W83194BR-703/W83194BG-703

9.7 PCI Electrical Characteristics

VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

MIN

500

MAX

2000

250

UNITS

ps

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

Fall Time

ps

Cycle to Cycle jitter

Duty Cycle

ps

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

9.8 24M, 48M Electrical Characteristics

VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

MIN

500

MAX

2000

500

UNITS

ps

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

Fall Time

ps

Long term jitter

ps

Duty Cycle

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

9.9 REF Electrical Characteristics

VDDREF= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

MIN

1000

MAX

4000

1000

55

UNITS

ps

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

Fall Time

ps

Cycle to Cycle jitter

Duty Cycle

ps

45

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

Publication Release Date: Jan. 2006

Revision 0.8

- 21 -

W83194BR-703/W83194BG-703

9.10 IOAPIC Electrical Characteristics

VDDI= 2.5V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

MIN

400

MAX

1600

500

UNITS

ps

TEST CONDITIONS

Measure from 0.4V to 2.0V

Measure from 2.0V to 0.4V

Measure 1.25V point

Fall Time

ps

Cycle to Cycle jitter

Duty Cycle

ps

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-27

mA

Vout=1.0V

Vout=2.375V

Vout=1.2V

Vout=0.3V

-27

30

27

10. ORDERING INFORMATION

PART NUMBER

PACKAGE TYPE

48 PIN SSOP

PRODUCTION FLOW

W83194BR-703

Commercial, 0°C to +70°C

48 PIN SSOP

W83194BG-703

Commercial, 0°C to +70°C

(Lead free package)

-22-

W83194BR-703/W83194BG-703

11. HOW TO READ THE TOP MARKING

W83194BG-703

28051234

W83194BR-703

28051234

342GAASA

442GAASA

1st line: Winbond logo and the type number:

Normal part :W83194BR-703, Lead free part: W83194BG-703

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 342 G A A SA

442: packages made in '2004, week 42

G: assembly house ID; O means OSE, G means GR

A: Internal use code

A: IC revision

SA: mask version

All the trademarks of products and companies mentioned in this data sheet belong to their respective

owners.

Publication Release Date: Jan. 2006

- 23 -

Revision 0.8

W83194BR-703/W83194BG-703

12. PACKAGE DRAWING AND DIMENSIONS

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

-24-

型号:	W83194BR-703
生命周期：	Obsolete
包装说明：	SSOP, SSOP48,.4
Reach Compliance Code：	compliant
风险等级：	5.8
JESD-30 代码：	R-PDSO-G48
端子数量：	48
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	2.5,3.3 V
认证状态：	Not Qualified
子类别：	Clock Generators
表面贴装：	YES
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
Base Number Matches：	1

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