W9864G6KH-6I全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

W9864G6KH

1M  4 BANKS  16 BITS SDRAM

Table of Contents-

1. GENERAL DESCRIPTION.............................................................................................................. 3

2. FEATURES...................................................................................................................................... 3

3. ORDER INFORMATION.................................................................................................................. 3

4. PIN CONFIGURATION.................................................................................................................... 4

5. PIN DESCRIPTION ......................................................................................................................... 5

6. BLOCK DIAGRAM........................................................................................................................... 6

7. FUNCTIONAL DESCRIPTION........................................................................................................ 7

7.1

Power Up and Initialization ................................................................................................. 7

Programming Mode Register.............................................................................................. 7

Bank Activate Command .................................................................................................... 7

Read and Write Access Modes .......................................................................................... 7

Burst Read Command ........................................................................................................ 8

Burst Write Command......................................................................................................... 8

Read Interrupted by a Read................................................................................................ 8

Read Interrupted by a Write................................................................................................ 8

Write Interrupted by a Write................................................................................................ 8

Write Interrupted by a Read................................................................................................ 8

Burst Stop Command.......................................................................................................... 8

Addressing Sequence of Sequential Mode......................................................................... 9

Addressing Sequence of Interleave Mode.......................................................................... 9

Auto-precharge Command................................................................................................ 10

Precharge Command........................................................................................................ 10

Self Refresh Command..................................................................................................... 10

Power Down Mode............................................................................................................ 11

No Operation Command................................................................................................... 11

Deselect Command .......................................................................................................... 11

Clock Suspend Mode........................................................................................................ 11

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.20

8. OPERATION MODE...................................................................................................................... 12

9. ELECTRICAL CHARACTERISTICS ............................................................................................. 13

9.1

9.2

9.3

9.4

9.5

Absolute Maximum Ratings .............................................................................................. 13

Recommended DC Operating Conditions ........................................................................ 13

Capacitance ...................................................................................................................... 13

DC Characteristics............................................................................................................ 14

AC Characteristics and Operating Condition.................................................................... 15

10. TIMING WAVEFORMS.................................................................................................................. 17

10.1

10.2

10.3

10.4

Command Input Timing..................................................................................................... 17

Read Timing...................................................................................................................... 18

Control Timing of Input/Output Data................................................................................. 19

Mode Register Set Cycle .................................................................................................. 20

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

11. OPERATING TIMING EXAMPLE.................................................................................................. 21

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3).......................................... 21

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)............... 22

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3).......................................... 23

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)............... 24

Interleaved Bank Write (Burst Length = 8) ....................................................................... 25

Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26

Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................... 27

Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28

Auto Precharge Read (Burst Length = 4, CAS Latency = 3)............................................ 29

11.10 Auto Precharge Write (Burst Length = 4) ......................................................................... 30

11.11 Auto Refresh Cycle........................................................................................................... 31

11.12 Self Refresh Cycle ............................................................................................................ 32

11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ................................. 33

11.14 Power Down Mode............................................................................................................ 34

11.15 Auto-precharge Timing (Write Cycle) ............................................................................... 35

11.16 Auto-precharge Timing (Read Cycle) ............................................................................... 36

11.17 Timing Chart of Read to Write Cycle ................................................................................ 37

11.18 Timing Chart of Write to Read Cycle ................................................................................ 37

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38

11.20 Timing Chart of Burst Stop Cycle (Precharge Command)................................................ 38

11.21 CKE/DQM Input Timing (Write Cycle) .............................................................................. 39

11.22 CKE/DQM Input Timing (Read Cycle) .............................................................................. 40

12. PACKAGE SPECIFICATION......................................................................................................... 41

13. REVISION HISTORY..................................................................................................................... 42

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

1. GENERAL DESCRIPTION

W9864G6KH is a high-speed synchronous dynamic random access memory (SDRAM), organized as

1M words  4 banks  16 bits. W9864G6KH delivers a data bandwidth of up to 200M words per

second. For different application, W9864G6KH is sorted into the following speed grades: -5, -6, -6I

and -7. The -5 grade parts can run up to 200MHz/CL3. The -6 and -6I grade parts can run up to

166MHz/CL3 (the -6I industrial grade which is guaranteed to support -40°C ~ 85°C). The -7 grade

parts can run up to 143MHz/CL3 and with t_RP= 18nS.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle.

The multiple bank nature enables interleaving among internal banks to hide the precharging time.By

having a programmable Mode Register, the system can change burst length, latency cycle, interleave

or sequential burst to maximize its performance. W9864G6KH is ideal for main memory in high

performance applications.

2. FEATURES



3.3V ± 0.3V for -5, -6 and -6I speed grades power supply

2.7V~3.6V for -7 speed grades power supply

Up to 200 MHz Clock Frequency

1,048,576 words 4 banks  16 bits organization

Self Refresh Current: Standard and Low Power

CAS Latency: 2 and 3

Burst Length: 1, 2, 4, 8 and full page

Sequential and Interleave Burst

Byte Data Controlled by LDQM, UDQM

Auto-precharge and Controlled Precharg

Burst Read, Single Writes Mode

4K Refresh Cycles/64 mS

Interface: LVTTL

Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant

3. ORDER INFORMATION

SELF REFRESH

CURRENT (MAX)

OPERATING

TEMPERATURE

PART NUMBER

SPEED GRADE

W9864G6KH-5

W9864G6KH-6

W9864G6KH-6I

W9864G6KH-7

200MHz/CL3

166MHz/CL3

143MHz/CL3

2mA

0°C ~ 70°C

-40°C ~ 85°C

0°C ~ 70°C

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

4. PIN CONFIGURATION

VDD

DQ0

VSS

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

1

2

DQ15

VSSQ

DQ14

DQ13

VDDQ

3

VDDQ

DQ1

4

DQ2

5

VSSQ

6

DQ12

DQ11

VSSQ

DQ3

7

DQ4

8

VDDQ

9

DQ10

DQ9

DQ5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DQ6

VSSQ

VDDQ

DQ8

DQ7

VDD

VSS

NC

LDQM

WE

UDQM

CLK

CKE

NC

CAS

RAS

CS

A11

A9

BS0

BS1

A10/AP

A0

A8

A7

A6

A1

A5

A2

A4

A3

VDD

VSS

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

5. PIN DESCRIPTION

PIN NUMBER PIN NAME

FUNCTION

DESCRIPTION

Multiplexed pins for row and column address.

Row address: A0A11. Column address: A0A7.

2326, 22,

A0A11

2935

Address

A10 is sampled during a precharge command to

determine if all banks are to be precharged or bank

selected by BS0, BS1.

Select bank to activate during row address latch time,

or bank to read/write during address latch time.

20, 21

BS0, BS1

Bank Select

2, 4, 5, 7, 8,

10, 11, 13, 42,

44, 45, 47, 48,

50, 51, 53

Data

Multiplexed pins for data output and input.

DQ0DQ15

Input/ Output

Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

19

18

Chip Select

CS

Command input. When sampled at the rising edge of

Row Address

Strobe

RAS

the clock, RAS ,

CAS and WE define the

operation to be executed.

Column Address

Strobe

17

16

CAS

WE

Referred to RAS

Write Enable

Referred to RAS

The output buffer is placed at Hi-Z (with latency of 2)

when DQM is sampled high in read cycle. In write

cycle, sampling DQM high will block the write

operation with zero latency.

LDQM,

UDQM

Input/Output

Mask

39, 15

System clock used to sample inputs on the rising edge

of clock.

38

37

CLK

CKE

Clock Inputs

CKE controls the clock activation and deactivation.

Clock Enable When CKE is low, Power Down mode, Suspend mode

or Self Refresh mode is entered.

1, 14, 27

VDD

VSS

Power

Power for input buffers and logic circuit inside DRAM.

Ground for input buffers and logic circuit inside DRAM.

28, 41, 54

Ground

Power for I/O Separated power from VDD, to improve DQ noise

Buffer immunity.

3, 9, 43, 49

VDDQ

Ground for I/O Separated ground from VSS, to improve DQ noise

Buffer immunity.

6, 12, 46, 52

36, 40

VSSQ

NC

No Connection No connection.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

6. BLOCK DIAGRAM

CLK

CLOCK

BUFFER

CKE

CONTROL

CS

SIGNAL

GENERATOR

RAS

COMMAND

CAS

DECODER

COLUMN DECODER

WE

A10

CELL ARRAY

BANK #0

CELL ARRAY

BANK #1

MODE

REGISTER

A0

SENSE AMPLIFIER

ADDRESS

BUFFER

A9

A11

BS0

BS1

DQ0

DATA CONTROL

CIRCUIT

DQ

BUFFER

DQ15

COLUMN

REFRESH

COUNTER

UDQM

LDQM

COUNTER

COLUMN DECODER

CELL ARRAY

BANK #2

CELL ARRAY

BANK #3

SENSE AMPLIFIER

NOTE:

The cell array configuration is 4096 * 256 * 16

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

7. FUNCTIONAL DESCRIPTION

7.1 Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and

initialization sequence need to be followed to guarantee the device being preconditioned to each user

specific needs.

During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage

when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD +0.3V

on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed

by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus

during power up, it is required that the DQM and CKE pins be held high during the initial pause period.

Once all banks have been precharged, the Mode Register Set Command must be issued to initialize

the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after

programming the Mode Register to ensure proper subsequent operation.

7.2 Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.

All banks must be in a precharged state and CKE must be high at least one cycle before the Mode

Register Set Command can be issued. The Mode Register Set Command is activated by the low

signals of RAS

CAS CS and WE at the positive edge of the clock. The address input data

, ,

during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A

new command may be issued following the mode register set command once a delay equal to t_RSC

has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

7.3 Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.

The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS

to CAS delay time (t_RCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive

Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t_RC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice

versa) is the Bank to Bank delay time (t_RRD). The maximum time that each bank can be held active is

specified as t_RAS(max).

7.4 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS high and CAS low at the clock rising edge after minimum of t_RCDdelay. WE pin voltage level

defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The

address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a

new Bank Activate command be issued. When more than one bank is activated, interleaved bank

Read or Write operations are possible. By using the programmed burst length and alternating the

access and precharge operations between multiple banks, seamless data access operation among

many different pages can be realized. Read or Write Commands can also be issued to the same bank

or between active banks on every clock cycle.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

7.5 Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding

RAS and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst

length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page

explain the address sequence of interleave mode and sequential mode.

7.6 Burst Write Command

The Burst Write command is initiated by applying logic low level to CS

,

CAS and WE while

holding RAS high at the rising edge of the clock. The address inputs determine the starting column

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle

that the Write Command is issued. The remaining data inputs must be supplied on each subsequent

rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes

will be ignored.

7.7 Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,

the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS Latency from the

interrupting Read Command the is satisfied.

7.8 Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output

drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will

issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the

DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM

masking is no longer needed.

7.9 Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the

previous burst is interrupted, the remaining addresses are overridden by the new address and data

will be written into the device until the programmed burst length is satisfied.

7.10 Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read

Command is activated. The DQs must be in the high impedance state at least one cycle before the

new read data appears on the outputs to avoid data contention. When the Read Command is

activated, any residual data from the burst write cycle will be ignored.

7.11 Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open

for future Read or Write Commands to the same page of the active bank, if the burst length is full page.

Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having RAS and CAS high with CS and WE low at the rising edge of

the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency

in a burst read cycle interrupted by Burst Stop.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

7.12 Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to

the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

ACCESS ADDRESS

BURST LENGTH

n

BL = 2 (disturb address is A0)

No address carry from A0 to A1

BL = 4 (disturb addresses are A0 and A1)

No address carry from A1 to A2

n + 1

n + 2

n + 3

n + 4

n + 5

n + 6

n + 7

BL = 8 (disturb addresses are A0, A1 and A2)

No address carry from A2 to A3

7.13 Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit

in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA

Data 0

Data 1

ACCESS ADDRESS

BURST LENGTH

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 2

A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

BL = 4

BL = 8

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

7.14 Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is

entered. During Auto-precharge, a Read Command will execute as normal with the exception that the

active bank will begin to precharge automatically before all burst read cycles have been completed.

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS Latency.

A Read or Write Command with auto-precharge can not be interrupted before the entire burst

operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is

prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,

the bank cannot be reactivated until the Precharge time (t_RP) has been satisfied. Issue of Auto-

Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write

Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically

enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred

to as write t_WR. The bank undergoing auto-precharge cannot be reactivated until t_WRand t_RPare

satisfied. This is referred to as t_DAL, Data-in to Active delay (t_DAL= t_WR+ t_RP). When using the Auto-

precharge Command, the interval between the Bank Activate Command and the beginning of the

internal precharge operation must satisfy t_RAS(min).

7.15 Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS

,

RAS and WE are low and CAS is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all

banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to

be precharged when the command is issued. After the Precharge Command is issued, the precharged

bank must be reactivated before a new read or write access can be executed. The delay between the

Precharge Command and the Activate Command must be greater than or equal to the Precharge time

(t_RP).

7.16 Self Refresh Command

The Self Refresh Command is defined by having CS

RAS CAS and CKE held low with WE

, ,

high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.

Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are

disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will

exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after

t_XSRfrom the end of Self Refresh Command.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and

just after exiting the self refresh mode.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

7.17 Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power Down mode does not perform any refresh operations,

therefore the device can not remain in Power Down mode longer than the Refresh period (t_REF) of the

device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation

Command is required on the next rising clock edge, depending on t_CK. The input buffers need to be

enabled with CKE held high for a period equal to t_CKS(min) + t_CK(min).

7.18 No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to

prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with RAS

,

CAS , and WE held high at the rising edge of

the clock. A No Operation Command will not terminate a previous operation that is still executing, such

as a burst read or write cycle.

7.19 Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect

Command occurs when CS is brought high, the RAS

cares.

,

CAS , and WE signals become don’t

7.20 Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low

while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode

deactivates the internal clock and suspends any clocked operation that was currently being executed.

There is a one clock delay between the registration of CKE low and the time at which the SDRAM

operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are

issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay

from when CKE returns high to when Clock Suspend mode is exited.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

8. OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 1 shows the truth table for the operation commands.

Table 1 Truth Table (Note (1), (2))

DEVICE

STATE

A0A9

COMMAND

Bank Active

CKEn-1 CKEn DQM BS0, 1 A10

CS RAS CAS

WE

A11

Idle

Any

H

x

v

x

v

L

H

L

v

x

v

L

H

L

H

L

Bank Precharge

Precharge All

Write

Any

L

Active ⁽³⁾

H

Write with Auto-precharge

Active ⁽³⁾

H

x

v

H

v

L

H

L

Read

Active ⁽³⁾

Idle

H

x

H

L

x

v

x

L

H

v

x

v

x

L

H

L

H

L

H

x

H

L

Read with Auto-precharge

Mode Register Set

No – Operation

Burst Stop

Any

H

x

H

L

Active ⁽⁴⁾

Any

Device Deselect

Auto - Refresh

Self - Refresh Entry

x

Idle

L

H

Idle

L

idle

L

H

x

H

L

x

Self Refresh Exit

(S.R.)

H

Clock suspend Mode Entry

Power Down Mode Entry

Active

H

L

x

Idle

Active ⁽⁵⁾

H

L

x

H

L

x

H

Clock Suspend Mode Exit

Power Down Mode Exit

Data write/Output Enable

Active

L

H

x

Any

L

H

x

H

L

x

(power down)

H

Active

H

x

L

x

Data Write/Output Disable

H

Notes:

(1) v = valid x = Don’t care L = Low Level H = High Level

(2) CKEn signal is input level when commands are provided.

CKEn-1 signal is the input level one clock cycle before the command is issued.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings

PARAMETER

Voltage on any pin relative to VSS

Voltage on VDD/VDDQ supply relative to VSS

Operating Temperature for -5/-6/-7

Operating Temperature for -6I

Storage Temperature

SYMBOL

RATING

UNIT NOTES

-1 ~ VDD + 0.5 (≤ 4.6V max.)

V

1

VIN, VOUT

VDD, VDDQ

TOPR

-1 ~ 4.6

0 ~ 70

-40 ~ 85

-55 ~ 150

260

°C

W

TOPR

TSTG

Soldering Temperature (10s)

Power Dissipation

TSOLDER

PD

1

Short Circuit Output Current

50

mA

IOUT

Note:

1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of

the device

9.2 Recommended DC Operating Conditions

PARAMETER

SYM.

MIN.

TYP.

MAX.

UNIT NOTES

Power Supply Voltage for -5/-6/-6I

Power Supply Voltage for -7

VDD

VDDQ

VIH

3.0

2.7

3.0

2.7

2.0

-0.3

3.3

3.6

V

2

-

Power Supply Voltage for -5/-6/-6I (for I/O Buffer)

Power Supply Voltage for -7 (for I/O Buffer)

Input High Voltage

3.3

3.6

-

3.6

VDD + 0.3

0.8

Input Low Voltage

VIL

Note: VIH(max) = VDD/ VDDQ+1.5V for pulse width ≤ 5 nS.

VIL(min) = VSS/ VSSQ-1.5V for pulse width ≤ 5 nS

9.3 Capacitance

(VDD = 3.3V ± 0.3V, TA = 25°C, f = 1 MHz)

PARAMETER

SYM.

Ci1

MIN.

MAX.

UNIT

Input Capacitance

2.5

4

pf

(A0 to A11, BS0, BS1, CS

Input Capacitance (CLK)

RAS CAS

, , ,

WE , CKE)

pf

2.5

4

CCLK

CO

Input/Output capacitance (DQ0DQ15)

6.5

5.5

Input Capacitance DQM

3.0

Ci2

Note: These parameters are periodically sampled and not 100% tested.

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

9.4 DC Characteristics

(VDD = 3.3V ± 0.3V for-5/-6 ,VDD = 2.7V~3.6V for -7 on TA = 0°C~70°C, VDD =3.3V ± 0.3V for -6I on TA = -40°C~85°C)

MAX.

PARAMETER

SYM.

UNIT

NOTES

-5

-6/-6I

-7

Operating Current

t_CK= min., t_RC= min.

Active precharge command

cycling without burst operation

1 Bank operation

CKE = VIH

IDD1

55

50

45

3

Standby Current

IDD2

IDD2P

IDD2S

30

2

25

2

20

2

3

tCK = min., CS = VIH

VIH/L = VIH (min.)/VIL (max.)

CKE = VIL

Bank: Inactive state

Standby Current

(Power Down Mode)

CKE = VIH

12

CLK = VIL, CS = VIH

VIH/L=VIH (min.)/VIL (max.)

CKE = VIL

Bank: Inactive state

IDD2PS

IDD3

2

(Power Down Mode)

mA

No Operating Current

CKE = VIH

40

12

35

12

30

12

t_CK= min., CS = VIH(min)

CKE = VIL

Bank: Active state (4 Banks)

IDD3P

(Power Down Mode)

Burst Operating Current

IDD4

80

75

70

3, 4

3

t_CK= min.

Read/ Write command cycling

Auto Refresh Current

IDD5

IDD6

65

2

60

2

55

2

t_CK= min.

Auto refresh command cycling

Self Refresh Current

Self Refresh Mode

CKE = 0.2V

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

NOTES

Input Leakage Current

II(L)

-5

5

µA

(0V ≤ VIN ≤ VDD, all other pins not under test = 0V)

Output Leakage Current

lO(L)

VOH

VOL

-5

2.4

-

µA

V

(Output disable, 0V ≤ VOUT ≤ VDDQ)

LVTTL Output “H” Level Voltage

-

(IOUT = -2 mA)

LVTTL Output “L” Level Voltage

0.4

V

(IOUT = 2 mA)

Publication Release Date: Mar. 26, 2017

Revision: A03

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W9864G6KH

9.5 AC Characteristics and Operating Condition

(VDD = 3.3V ± 0.3V for-5/-6, VDD = 2.7V-3.6V for -7 on TA = 0°C~70°C, VDD = 3.3V ± 0.3V for -6I on TA = -40°C~85°C)

(Notes: 5, 6)

-5

-6/-6I

MAX.

-7

PARAMETER

SYM.

UNIT NOTES

MIN.

MAX.

MIN.

MIN. MAX.

Ref/Active to Ref/Active Command

Period

55

60

65

t_RC

t_RAS

t_RCD

Active to precharge Command Period

40 100000 42 100000 45 100000 nS

Active to Read/Write Command Delay

Time

15

1

15

1

20

1

Read/Write(a) to Read/Write(b)

Command Period

t_CCD

t_CK

Precharge to Active Command Period

Active(a) to Active(b) Command Period

15

2

15

2

20

2

nS

t_CK

t_RP

t_RRD

CL* = 2

Write Recovery Time

CL* = 3

2

t_WR

t_CK

2

CL* = 2

CLK Cycle Time

10

5

1000

7.5

6

1000

10

7

1000

CL* = 3

2

8

CLK High Level width

CLK Low Level width

t_CH

t_CL

2

CL* = 2

Access Time from CLK

CL* = 3

6

5

6

9

7

9

t_AC

t_OH

t_HZ

4.5

5.5

Output Data Hold Time

3

CL* = 2

CL* = 3

6

5

6

Output Data High

Impedance Time

4.5

5.5

Output Data Low Impedance Time

Power Down Mode Entry Time

Transition Time of CLK (Rise and Fall)

Data-in Set-up Time

0

t_LZ

t_SB

nS

5

1

6

1

7

1

t_T

1.5

1

1.5

1

1.5

1

8

t_DS

Data-in Hold Time

t_DH

Address Set-up Time

1.5

1

1.5

1

1.5

1

t_AS

Address Hold Time

t_AH

CKE Set-up Time

1.5

1

1.5

1

1.5

1

t_CKS

t_CKH

t_CMS

t_CMH

t_REF

t_RSC

t_XSR

CKE Hold Time

Command Set-up Time

Command Hold Time

1.5

1

1.5

1

1.5

1

Refresh Time (4K Refresh Cycles)

Mode register Set Cycle Time

Exit self refresh to ACTIVE command

* CL = CAS Latency

64

mS

t_CK

nS

2

70

72

75

Publication Release Date: Mar. 26, 2017

Revision: A03

- 15 -

W9864G6KH

Notes:

1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.

2. All voltages are referenced to V_SS.

• 2.7V~3.6V power supply for -7 speed grades.

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the

minimum values of t_CKand t_RC.

4. These parameters depend on the output loading conditions. Specified values are obtained with

output open.

5. Power up sequence please refer to “Functional Description” section described before.

6. AC test load diagram.

1.4 V

50 ohms

output

Z = 50 ohms

30pF

ACTEST LOAD

7. t_HZdefines the time at which the outputs achieve the open circuit condition and is not referenced to

output level.

8. Assumed input rise and fall time (t_T) = 1nS.

If tr & tf is longer than 1nS, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]nS should be added to the parameter

9. If clock rising time (t_T) is longer than 1nS, (t_T/2-0.5)nS should be added to the parameter.

Publication Release Date: Mar. 26, 2017

Revision: A03

- 16 -

W9864G6KH

10. TIMING WAVEFORMS

10.1 Command Input Timing

tCK

tCL

tCH

VIH

CLK

VIL

tT

tCMS

tCMH

tCMS

tCMH

CS

tCMS

RAS

tCMS

tCMH

tAH

CAS

tCMS

WE

tAS

A0-A11

BS0,1

tCKS

tCKH

tCKS

tCKH

tCKS

tCKH

CKE

Publication Release Date: Mar. 26, 2017

Revision: A03

- 17 -

W9864G6KH

10.2 Read Timing

Read CAS Latency

CLK

CS

RAS

CAS

WE

A0-A11

BS0,1

tHZ

tAC

tOH

tLZ

tOH

Valid

Data-Out

Valid

Data-Out

DQ

Read Command

Burst Length

Publication Release Date: Mar. 26, 2017

Revision: A03

- 18 -

W9864G6KH

10.3 Control Timing of Input/Output Data

Control Timing of Input Data

(Word Mask)

CLK

tCMH

tCMS

tCMH

tCMS

tDS

DQM

tDS

tDH

tDS

tDH

tDS

tDH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ0~15

(Clock Mask)

CLK

tCKH

tCKS

tDS

tCKH

tDH

tCKS

CKE

tDH

tDS

tDH

tDS

tDH

tDS

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ0~15

Control Timing of Output Data

(Output Enable)

CLK

tCMS

tCMH

tCMS

tCMH

DQM

tAC

tOH

tAC

tHZ

tOH

tAC

tLZ

tOH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ0~15

OPEN

(Clock Mask)

CLK

tCKS

tCKH

tCKS

tCKH

CKE

tAC

tOH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ0~15

Publication Release Date: Mar. 26, 2017

Revision: A03

- 19 -

W9864G6KH

10.4 Mode Register Set Cycle

tRSC

CLK

tCMS

tCMH

CS

RAS

CAS

WE

tCMS

tAS

tCMH

tAH

Register

set data

A0-A11

BS0,1

Burst Length

A0

A1

A2

A3

A4

A5

A6

Sequential

A2 AA10 A0

Interleave

Burst Length

0

1

A00

A10

A00

A0

0

A10

0

1

0

1

0

1

0

1

2

4

8

1

2

4

8

Addressing Mode

CAS Latency

"0"

(Test Mode)

Reserved

Full Page

Reserved

Addressing Mode

A03

0

1

Sequential

Interleave

A07

A8

"0"

Reserved

WriteAM0 ode

CAS Latency

Reserved

2

A6 AA50 A4

0

1

A00

A10

A00

0

1

0

1

0

A9

A10

AA101

BS0

BS1

"0"

3

Reserved

"0"

Single Write Mode

Burst read and Burst write

Burst read and single write

A90

0

1

* "Reserved" should stay "0" during MRS cycle.

Publication Release Date: Mar. 26, 2017

Revision: A03

- 20 -

W9864G6KH

11. OPERATING TIMING EXAMPLE

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

1

2

3

4

5

0

CLK

CS

tRC

RAS

CAS

tRP

tRAS

tRP

tRAS

tRP

tRAS

WE

BS0

BS1

A10

tRCD

RBb

RAa

RAe

RAc

RBd

A0-A9,

A11

CAw

CBx

RBb

RAc

CAy

CBz

DQM

CKE

tAC

bx3

cy0 cy1

cy2 cy3

aw0 aw1 aw2 aw3

bx1 bx2

bx0

DQ

tRRD

Precharge

Read

Active

Read

Bank #0

Active

Read

Precharge

Bank #1

Bank #2

Bank #3

Active

Read

Active

Idle

Publication Release Date: Mar. 26, 2017

Revision: A03

- 21 -

W9864G6KH

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)

11

12

13

14

15

16

17

18

19

20

21

22

23

1

2

3

4

5

6

7

8

9

10

0

CLK

CS

tRC

RAS

CAS

WE

tRAS

tRP

tRAS

tRP

tRAS

BS0

BS1

tRCD

RAa

RBb

RBd

RAc

RAe

A10

A0-A9,

A11

RAa

CAw RBb

CBx

RAc

CAy

RBd

CBz

RAe

DQM

CKE

tAC

aw2 aw3

aw0 aw1

bx0 bx1 bx2 bx3

cy0 cy1 cy2 cy3

dz0

DQ

tRRD

Bank #0

Bank #1

Bank #2

Bank #3

Active

AP*

Active

Read

AP*

Active

Read

AP*

Active

Read

Active

Read

Idle

* AP is the internal precharge start timing

Publication Release Date: Mar. 26, 2017

Revision: A03

- 22 -

W9864G6KH

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

8

9

10 11 12 13 14 15 16 17 18

1

2

3

4

5

6

7

19 20 21 22 23

0

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

WE

BS0

BS1

A10

tRCD

RAa

RBb

RAc

A0-A9,

A11

CAx

CBy

CAz

DQM

CKE

tAC

ax6

tAC

by4

by5

by6

by7

CZ0

ax0

ax1

ax2

ax3

ax4

ax5

by0

by1

DQ

tRRD

Bank #0

Read

Active

Precharge

Active

Read

Bank #1

Bank #2

Bank #3

Precharge

Active

Read

Precharge

Idle

Publication Release Date: Mar. 26, 2017

Revision: A03

- 23 -

W9864G6KH

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)

6

7

8

9

10

11

12

13

14

15 16

17

18

19

20

1

2

3

4

5

21

22 23

0

CLK

CS

tRC

RAS

tRAS

tRP

tRAS

tRP

CAS

WE

BS0

BS1

tRCD

RAc

RAa

RBb

A10

A0-A9,

A11

CAx

CBy

RAc

CAz

DQM

CKE

tAC

ax3

ax4

ax5

ax6

ax7

by0

by1

by4

by5

by6

CZ0

ax0

ax1

ax2

DQ

tRRD

Bank #0 Active

Bank #1

Read

AP*

Active

Read

Active

Read

AP*

Bank #2

Idle

Bank #3

* AP is the internal precharge start timing

Publication Release Date: Mar. 26, 2017

Revision: A03

- 24 -

W9864G6KH

11.5 Interleaved Bank Write (Burst Length = 8)

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

1

2

3

4

5

0

CLK

CS

tRC

RAS

CAS

WE

tRAS

tRP

tRAS

tRCD

BS0

BS1

RBb

RAc

RAa

A10

A0-A9,

A11

CAx

RBb

CBy

RAc

CAz

DQM

CKE

ax0

ax1

ax4

ax5

ax6

ax7

by0

by1

by2

by3

CZ2

by4

by5

by6

by7

CZ0

CZ1

DQ

tRRD

Active

Bank #0

Precharge

Write

Active

Write

Bank #1

Bank #2

Bank #3

Active

Precharge

Idle

Publication Release Date: Mar. 26, 2017

Revision: A03

- 25 -

W9864G6KH

11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

tRC

RAS

CAS

tRP

tRAS

WE

BS0

BS1

A10

tRCD

RAa

RBb

RAb

A0-A9,

A11

CAx

CBy

RAc

CAz

DQM

CKE

ax0

ax1

ax4

ax5

ax6

ax7

by0

by1 by2 by3

by4

by5

by6

by7 CZ0

CZ1

CZ2

DQ

tRRD

AP*

Write

AP*

Active

Idle

Write

Bank #0

Bank #1

Bank #2

Bank #3

Active

* AP is the internal precharge start timing

Publication Release Date: Mar. 26, 2017

Revision: A03

- 26 -

W9864G6KH

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

tCCD

tRAS

RAS

CAS

WE

BS0

BS1

A10

tRCD

RAa

RBb

A0-A9,

A11

CAI RBb

CBx

CAy

CAm

CBz

DQM

CKE

tAC

a0

a1

a2

a3

bx0

bx1

Ay0

Ay1 Ay2 am0 am1 am2

bz0

bz1

bz2

bz3

DQ

tRRD

Read

Bank #0 Active

Bank #1

Read

Precharge

AP*

Active

Read

Bank #2

Idle

Bank #3

* AP is the internal precharge start timing

Publication Release Date: Mar. 26, 2017

Revision: A03

- 27 -

W9864G6KH

11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRAS

RAS

CAS

WE

BS0

BS1

A10

tRCD

RAa

A0-A9,

A11

CAx

CAy

DQM

CKE

tAC

tWR

ay1

ay0

ay2

ay3

ay4

ax0

ax1

ax2

ax3

ax4

ax5

DQ

Q

D

Precharge

Bank #0

Bank #1

Bank #2

Bank #3

Active

Read

Write

Idle

Publication Release Date: Mar. 26, 2017

Revision: A03

- 28 -

W9864G6KH

11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRC

RAS

tRAS

tRP

tRAS

CAS

WE

BS0

BS1

A10

tRCD

RAa

RAb

A0-A9,

A11

CAx

RAa

CAw

RAb

DQM

CKE

tAC

aw0

aw1 aw2 aw3

bx0

bx1

bx2

bx3

DQ

AP*

Bank #0

Bank #1

Bank #2

Bank #3

Active

Read

Active

Read

AP*

Idle

* AP is the internal precharge start timing

Publication Release Date: Mar. 26, 2017

Revision: A03

- 29 -

W9864G6KH

11.10 Auto Precharge Write (Burst Length = 4)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

tRP

WE

BS0

BS1

tRCD

RAb

RAc

RAa

A10

A0-A9,

A11

CAw

RAb

CAx

RAc

DQM

CKE

aw0 aw1 aw2 aw3

bx0

bx1 bx2

bx3

DQ

Bank #0

Bank #1

Bank #2

Bank #3

Active

Write

AP*

Active

Write

AP*

Active

Idle

* AP is the internal precharge start timing

Publication Release Date: Mar. 26, 2017

Revision: A03

- 30 -

W9864G6KH

11.11 Auto Refresh Cycle

6

7

8

11 12 13

16 17 18

1

2

3

5

9

10

14 15

19

21

0

4

20

22 23

CLK

CS

tRP

tRC

RAS

CAS

WE

BS0,1

A10

A0-A9,

A11

DQM

CKE

DQ

All Banks

Prechage

Auto

Refresh

Auto Refresh (Arbitrary Cycle)

Publication Release Date: Mar. 26, 2017

Revision: A03

- 31 -

W9864G6KH

11.12 Self Refresh Cycle

CLK

CS

tRP

RAS

CAS

WE

BS0,1

A10

A0-A9,

A11

DQM

tCKS

tSB

CKE

tCKS

DQ

tXSR

Self Refresh Cycle

No Operation / Command Inhibit

All Banks

Precharge

Self Refresh

Entry

Self Refresh

Exit

Arbitrary Cycle

Publication Release Date: Mar. 26, 2017

Revision: A03

- 32 -

W9864G6KH

11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CS

RAS

CAS

WE

t^RCD

BS0

BS1

A10

RBa

A0-A9,

A11

RBa

CBv

CBw

CBx CBy CBz

DQM

CKE

t^AC

tAC

av0

av1

av2

av3

aw0

ax0

ay0

az0

az1

az2

az3

DQ

Q

D

Q

Active

Read

Single Write Read

Bank #0

Bank #1

Bank #2

Bank #3

Idle

Publication Release Date: Mar. 26, 2017

Revision: A03

- 33 -

W9864G6KH

11.14 Power Down Mode

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CLK

CS

RAS

CAS

WE

BS

RAa

A10

A0-A9,

A11

CAa

CAx

DQM

CKE

tSB

tCKS

ax0

ax1

ax2

ax3

DQ

Active

NOP Read

Precharge

NOP Active

Precharge Standby

Power Down mode

Active Standby

Power Down mode

Note: The Power Down Mode is entered by asserting CKE "low".

All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.

When CKE goes high, command input must be No operation at next CLK rising edge.

Violating refresh requirements during power-down may result in a loss of data.

Publication Release Date: Mar. 26, 2017

Revision: A03

- 34 -

W9864G6KH

11.15 Auto-precharge Timing (Write Cycle)

0

1

2

3

4

5

6

7

8

9

10

11

12

CLK

(1) CAS Latency= 2

(a) burst length = 1

Command

Write

D0

AP

Act

tWR

tRP

DQ

(b) burst length = 2

Command

Write

D0

AP

Act

AP

tWR

tRP

DQ

D1

(c) burst length = 4

Command

Act

D7

Write

D0

tRP

tWR

DQ

D2

D3

(d) burst length = 8

Command

Write

D0

AP

Act

tWR

tRP

DQ

D1

D2

AP

D4

D5

Act

D6

(2) CAS Latency= 3

(a) burst length = 1

Command

Write

D0

tWR

tRP

DQ

(b) burst length = 2

Command

Write

D0

AP

Act

tWR

tRP

DQ

D1

(c) burst length = 4

Command

Write

D0

AP

D5

Act

tWR

tRP

DQ

D2

D3

(d) burst length = 8

Command

Write

D0

AP

Act

tWR

tRP

DQ

D4

D6

D7

Note )

represents the Write with Auto precharge command.

represents the start of internal precharing.

represents the BankActive command.

Write

AP

Act

When the /auto precharge command is asserted,the period from BankActivate

command to the start of intermal precgarging must be at least tRAS (min).

Publication Release Date: Mar. 26, 2017

Revision: A03

- 35 -

W9864G6KH

11.16 Auto-precharge Timing (Read Cycle)

0

1

2

3

4

5

6

7

8

9

10

11

(1) CAS Latency=2

( a ) burst length = 1

Command

Read AP

Read

Act

t

RP

DQ

Q0

( b ) burst length = 2

Command

AP

Q0

Act

t

RP

DQ

Q1

( c ) burst length = 4

Command

Read

AP

Q2

Act

Q4

t

RP

DQ

Q0

Q1

Q3

( d ) burst length = 8

Command

Read

AP

Q6

Act

t

RP

DQ

Q2

Act

Q3

Act

Q5

Q7

(2) CAS Latency=3

( a ) burst length = 1

Command

Read AP

Read

t

RP

DQ

Q0

( b ) burst length = 2

Command

AP

t

RP

DQ

Q1

AP

Q1

( c ) burst length = 4

Command

Read

Act

Q4

t

RP

DQ

Q2

Q3

( d ) burst length = 8

Command

Read

AP

Q5

Act

t

RP

DQ

Q1

Q6

Q7

Note )

Read

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at leas (min).

RtAtS

Publication Release Date: Mar. 26, 2017

Revision: A03

- 36 -

W9864G6KH

11.17 Timing Chart of Read to Write Cycle

In the case of Burst Length = 4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

(a)Command

Read Write

DQM

DQ

D0

D1

D2

D1

D3

D2

(b)Command

DQM

Read

Write

D0

D3

DQ

(2) CAS Latency=3

(a)Command

DQM

Read Write

DQ

D0

D1

D2

D1

D3

D2

(b)Command

Read

Write

DQM

DQ

D0

D3

Note: The Output data must be masked by DQMto avoid I/O conflict

11.18 Timing Chart of Write to Read Cycle

In the case of Burst Length=4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

Write Read

(a)Command

DQM

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

(b)Command

DQM

Read

Write

DQ

D0

D1

Q3

(2) CAS Latency=3

(a)Command

DQM

Write Read

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

(b)Command

DQM

Write

Read

DQ

Q3

D0

D1

Publication Release Date: Mar. 26, 2017

Revision: A03

- 37 -

W9864G6KH

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)

0

1

2

3

4

5

6

7

8

9

10

11

(1) Read cycle

( a ) CAS latency =2

Command

Read

BST

Q3

DQ

Q0

Q1

Q0

Q2

Q1

Q4

Q3

( b )CAS latency = 3

Command

Read

BST

Q2

DQ

Q4

(2) Write cycle

Command

Write

Q0

BST

DQ

Q1

Q2

Q3

Q4

Note: BST

represents the Burst stop command

11.20 Timing Chart of Burst Stop Cycle (Precharge Command)

0

1

2

3

4

5

6

7

8

9

10

11

(1) Read cycle

(a) CAS latency =2

Command

Read

PRCG

Q3

DQ

Q0

Q1

Q0

Q2

Q1

Q4

Q3

(b) CAS latency =3

Command

PRCG

Q2

DQ

Q4

(2) Write cycle

Write

Q0

PRCG

Command

tWR

DQM

DQ

Q1

Q2

Q3

Q4

Publication Release Date: Mar. 26, 2017

Revision: A03

- 38 -

W9864G6KH

11.21 CKE/DQM Input Timing (Write Cycle)

1

CLK cycle No.

2

3

4

5

7

6

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D5

D6

DQM MASK

CKE MASK

( 1 )

CLK cycle No.

External

2

3

4

5

7

1

6

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D6

D5

DQM MASK

( 2 )

CKE MASK

1

2

3

4

5

6

7

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D4

D5

D6

CKE MASK

( 3 )

Publication Release Date: Mar. 26, 2017

Revision: A03

- 39 -

W9864G6KH

11.22 CKE/DQM Input Timing (Read Cycle)

1

CLK cycle No.

2

3

4

5

6

7

External

CLK

Internal

CKE

DQM

DQ

Q6

Q1

1

Q2

Q3

Q4

Open

( 1 )

2

3

4

5

7

CLK cycle No.

External

6

CLK

Internal

CKE

DQM

DQ

Q3

Q4

Q6

Q1

1

Q2

Open

( 2 )

CLK cycle No.

2

3

4

5

6

7

External

CLK

Internal

CKE

DQM

DQ

Q6

Q3

Q1

Q5

Q4

Q2

( 3 )

Publication Release Date: Mar. 26, 2017

Revision: A03

- 40 -

W9864G6KH

12. PACKAGE SPECIFICATION

Package Outline TSOP (TYPE II) 54L 400 MIL (1:3)

54

28

E1

E

1

27

DETAIL “A”

e

b

RAD. R1

RAD. R

D

ZD

A2

A1

A

θ₁

θ

C

L

Y

SEATING PLANE

L1

DETAIL “A”

Controlling Dimension : Millimeters

DIMENSION

(INCH)

(MM)

SYMBOL

MIN.

NOM.

MAX.

MIN.

NOM.

MAX.

A

A1

A2

b

0.047

0.006

0.041

0.018

0.008

0.880

0.471

0.405

1.20

0.15

---

0.05

0.002

0.95

0.30

1.00

0.039

1.05

0.45

0.037

0.012

0.005

0.870

0.455

0.395

---

0.875

---

c

0.12

0.21

22.09

D

22.22

22.35

11.96

10.29

0.463

0.400

E

11.56

10.03

11.76

E1

e

10.16

0.80 BASIC

0.50

0.031 BASIC

0.020

0.40

0.60

0.024

L

0.016

L1

R

0.80 BASIC

0.031 BASIC

---

0.12

0.25

0.005

0.010

---

R1

---

0.71 REF

0.028 REF

ZD

θ

θ₁

Y

0°

8°

0°

8°

20°

---

15°

---

15°

10°

---

20°

0.10

0.004

---

Publication Release Date: Mar. 26, 2017

Revision: A03

- 41 -

W9864G6KH

13.

REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Initial formally datasheet

A01

A02

Aug. 07, 2013

All

Revise section 12 package outline drawing dimension

table symbol H1 to E1

Nov. 12, 2013

41

Update section 9.1 Absolute Maximum Ratings

Voltage on any pin relative to VSS (VIN, VOUT) and

Voltage on VDD/VDDQ supply relative to VSS (VDD,

VDDQ) minimum voltage from -0.5V to -1V

Jun. 01, 2016

Mar. 26, 2017

13

42

A03

Remove ”important notice”

Publication Release Date: Mar. 26, 2017

Revision: A03

- 42 -

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