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产品型号WM8524CGEDT的概述

芯片WM8524CGEDT的概述 WM8524CGEDT是英国Wolfson Microelectronics（现为Cirrus Logic的一部分）开发的一款高性能音频DAC（数模转换器）。它专为实现高保真音质和低功耗设计，广泛应用于便携式音频设备、消费者电子产品以及专业音频设备中。该芯片在音频处理领域表现出色，适合用于诸如音频播放器、家庭音响系统以及其他需要高质量音频输出的应用场景。芯片WM8524CGEDT的详细参数 WM8524CGEDT的主要技术参数如下： - 采样率: 支持高达192kHz的采样率。 - 位深: 提供16位和24位的音频数据处理能力，保证了高动态范围的音频输出。 - 总谐波失真+噪声（THD+N）: 优秀的音频质量，通常低于0.01%。 - 动态范围: 高达100dB，提供了更加丰富的音频细节。 - 工作电压: 常见的电源电压为+5V，适用于多种电源配置。...

产品型号WM8524CGEDT的Datasheet PDF文件预览

WM8524

24-bit 192kHz Stereo DAC with 2Vrms

Ground Referenced Line Output

DESCRIPTION

FEATURES



High performance stereo DAC with ground referenced line

driver

Audio Performance

The WM8524 is a stereo DAC with integral charge pump

and hardware control interface. This provides 2Vrms line

driver outputs using a single 3.3V power supply rail.





106dB SNR (‘A-weighted’)

-89dB THD @ -1dBFS

The device features ground-referenced outputs and the use

of a DC servo to eliminate the need for line driving coupling

capacitors and effectively eliminate power on pops and

clicks.



120dB mute attenuation

All common sample rates from 8kHz to 192kHz supported

Hardware control mode

Data formats: LJ, RJ, I²S

The device is controlled and configured via a hardware

control interface.

Maximum 1mV DC offset on Line Outputs

Pop/Click suppressed Power Up/Down Sequencer

AVDD and LINEVDD +3.3V ±10% allowing single supply

16-lead TSSOP package

The device supports all common audio sampling rates

between 8kHz and 192kHz using all common MCLK fs

rates. The audio interface operates in slave mode.

Operating temperature range: -40°C to 85°C

The WM8524 has a 3.3V tolerant digital interface, allowing

logic up to 3.3V to be connected.

APPLICATIONS



Consumer digital audio applications requiring 2Vrms output

The device is available in a 16-pin TSSOP.



Games Consoles

Set Top Box

A/V Receivers

DVD Players

Digital TV

BLOCK DIAGRAM

WOLFSON MICROELECTRONICS plc

Production Data, October 2011, Rev 4.1

To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews

WM8524

Production Data

TABLE OF CONTENTS

DESCRIPTION....................................................................................................... 1

FEATURES............................................................................................................ 1

APPLICATIONS..................................................................................................... 1

BLOCK DIAGRAM ................................................................................................ 1

TABLE OF CONTENTS......................................................................................... 2

PIN CONFIGURATION.......................................................................................... 3

ORDERING INFORMATION.................................................................................. 3

PIN DESCRIPTION................................................................................................ 4

ABSOLUTE MAXIMUM RATINGS........................................................................ 5

RECOMMENDED OPERATING CONDITIONS..................................................... 5

ELECTRICAL CHARACTERISTICS ..................................................................... 6

TERMINOLOGY .............................................................................................................. 6

POWER CONSUMPTION MEASUREMENTS................................................................ 7

SIGNAL TIMING REQUIREMENTS ...................................................................... 8

SYSTEM CLOCK TIMING............................................................................................... 8

AUDIO INTERFACE TIMING – SLAVE MODE ............................................................... 9

POWER ON RESET CIRCUIT ...................................................................................... 10

DEVICE DESCRIPTION ...................................................................................... 12

INTRODUCTION ........................................................................................................... 12

DIGITAL AUDIO INTERFACE....................................................................................... 12

DIGITAL AUDIO DATA SAMPLING RATES ................................................................. 14

HARDWARE CONTROL INTERFACE.......................................................................... 15

POWER UP AND DOWN CONTROL............................................................................ 16

POWER DOMAINS ....................................................................................................... 17

DIGITAL FILTER CHARACTERISTICS .............................................................. 18

DAC FILTER RESPONSES .......................................................................................... 19

APPLICATIONS INFORMATION ........................................................................ 20

RECOMMENDED EXTERNAL COMPONENTS ........................................................... 20

RECOMMENDED ANALOGUE LOW PASS FILTER.................................................... 21

RECOMMENDED PCB LAYOUT .................................................................................. 21

RELEVANT APPLICATION NOTES.............................................................................. 22

PACKAGE DIMENSIONS.................................................................................... 23

IMPORTANT NOTICE ......................................................................................... 24

ADDRESS ..................................................................................................................... 24

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Production Data

WM8524

PIN CONFIGURATION

ORDERING INFORMATION

ORDER CODE

WM8524CGEDT

WM8524CGEDT/R

TEMPERATURE

RANGE

PACKAGE

MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING

TEMPERATURE

−40°C to +85°C

16 lead TSSOP

(Pb-free)

MSL1

260^oC

−40°C to +85°C

16-lead TSSOP

(Pb-free, tape and reel)

MSL1

260^oC

Note:

Reel quantity = 2000

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PIN DESCRIPTION

PIN NO

NAME

LINEVOUTL

CPVOUTN

CPCB

TYPE

DESCRIPTION

Analogue Out

Left line output

Analogue Out

Supply

Charge Pump negative rail decoupling pin

Charge Pump fly back capacitor pin

Charge Pump ground

LINEGND

CPCA

Analogue Out

Supply

Charge Pump fly back capacitor pin

Charge Pump supply

LINEVDD

DACDAT

LRCLK

Digital In

Digital audio interface data input

Digital audio interface left/right clock

Digital audio interface bit clock

Master clock

Digital In

BCLK

Digital In

MCLK

0 = Mute enabled

1 = Mute disabled

Digital In

M¯¯U¯T¯E¯

0 = 24-bit Left Justified

1 = 24-bit I²S

Digital In

Tri-level

AIFMODE

Z = 24-bit Right Justified

Supply

Analogue Out

Supply

Analogue ground

AGND

VMID

Analogue midrail decoupling pin

Analogue supply

AVDD

Analogue Out

Right line output

LINEVOUTR

Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)

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WM8524

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously

operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given

under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically

susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling

and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

MIN

-0.3V

MAX

+4.5V

AVDD, LINEVDD

Voltage range digital inputs

Voltage range analogue inputs

Temperature range, T_A

LINEGND -0.3V

AGND -0.3V

-40°C

LINEVDD +0.3V

AVDD +0.3V

+125°C

Storage temperature after soldering

-65°C

+150°C

Notes:

1. Analogue grounds must always be within 0.3V of each other.

2. LINEVDD and AVDD must always be within 0.3V of each other.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Analogue supply range

Ground

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AVDD, LINEVDD

AGND, LINEGND

2.97

3.3

3.63

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WM8524

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ELECTRICAL CHARACTERISTICS

Test Conditions

LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, T_A=+25^°C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analogue Output Levels

Output Level

0dBFS

1.89

2.1

2.31

Vrms

kΩ

Load Impedance

Load Capacitance

No external RC filter

300

With filter shown in

Figure 16

µF

DAC Performance

Signal to Noise Ratio

SNR

R_L= 10kΩ

A-weighted

R_L= 10kΩ

Un-weighted

R_L= 10kΩ

A-weighted

-1dBFS

106

104

Dynamic Range

DNR

THD

Total Harmonic Distortion

-89

-86

0dBFS

AVDD + LINEVDD

PSRR

100Hz

Power Supply Rejection Ratio

1kHz

20kHz

Channel Separation

1kHz

100

20Hz to 20kHz

System Absolute Phase

Channel Level Matching

Mute Attenuation

degrees

0.1

-120

DC Offset at LINEVOUTL and

LINEVOUTR

-1

Digital Logic Levels

Input HIGH Level

V_IH

V_IL

0.7

LINEVDD

Input LOW Level

0.3

LINEVDD

Input Capacitance

Input Leakage

-0.9

0.9

A

TERMINOLOGY

1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale

output signal and the output with no input signal applied.

2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to

the amplitude of the measured output signal.

3. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to

use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The

low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with

mute applied.

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WM8524

POWER CONSUMPTION MEASUREMENTS

Test Conditions

LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, T_A=+25°C, Slave Mode, quiescent (no signal)

TEST CONDITIONS

IAVDD

(mA)

0.8

ILINEVDD

(mA)

TOTAL

(mA)

1.9

Off

No clocks applied

1.1

fs=48kHz, MCLK=256fs

Standby

M¯¯U¯T¯E¯ = 0

M¯¯U¯T¯E¯ = 1

0.2

4.8

2.2

6.0

2.4

Playback

10.8

fs=96kHz, MCLK=256fs

Standby

M¯¯U¯T¯E¯ = 0

M¯¯U¯T¯E¯ = 1

0.2

5.5

2.9

8.5

3.1

Playback

14.0

fs=192kHz, MCLK=128fs

Standby

M¯¯U¯T¯E¯ = 0

M¯¯U¯T¯E¯ = 1

0.2

5.5

2.9

8.5

3.1

Playback

14.0

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WM8524

Production Data

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T_A=+25°C

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Master Clock Timing Information

MCLK cycle time

t_MCLKY

t_MCLKH

t_MCLKL

500

MCLK high time

MCLK low time

MCLK duty cycle (t_MCLKH/t_MCLKL)

40:60

60:40

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WM8524

AUDIO INTERFACE TIMING – SLAVE MODE

t_BCY

BCLK

(input)

V_IH

V_IL

t_BCH

t_BCL

LRCLK

(input)

V_IH

V_IL

t_LRH

t_LRSU

DACDAT

(input)

V_IH

V_IL

t_DS

t_DH

Figure 2 Digital Audio Data Timing – Slave Mode

Test Conditions

LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T_A=+25^°C, Slave Mode

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

t_BCY

t_BCH

t_BCL

t_LRSU

t_LRH

t_DH

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK rising edge

LRCLK hold time from BCLK rising edge

DACDAT hold time from LRCLK rising edge

DACDAT set-up time to BCLK rising edge

t_DS

Table 1 Slave Mode Audio Interface Timing

Note:

BCLK period should always be greater than or equal to MCLK period.

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POWER ON RESET CIRCUIT

Figure 3 Internal Power on Reset Circuit Schematic

The WM8524 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is used to

reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD

and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a

minimum threshold.

Figure 4 Typical Power Timing Requirements

Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD

goes above the minimum threshold, V_pora, there is enough voltage for the circuit to guarantee POR is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. After VMID rises to V_{pord_hi}and AVDD rises to V_{pora_hi,}POR is released high and all registers

are in their default state and writes to the control interface may take place.

On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum

threshold V_{pora_low}

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WM8524

Test Conditions

LINEVDD = AVDD = 3.3V AGND = LINEGND = 0V, T_A= +25^oC

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply Input Timing Information

VDD level to POR defined

(LINEVDD/AVDD rising)

V_pora

Measured from LINEGND

158

0.8

VDD level to POR rising edge

(VMID rising)

V_{pord_hi}

V_{pora_hi}

V_{pora_lo}

0.63

1.44

0.96

VDD level to POR rising edge

(LINEVDD/AVDD rising)

1.8

2.18

1.97

VDD level to POR falling edge

(LINEVDD/AVDD falling)

1.46

Table 2 Power on Reset

Note: All values are simulated results

PD, Rev 4.1, October 2011

WM8524

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DEVICE DESCRIPTION

INTRODUCTION

The WM8524 provides high fidelity, 2Vrms ground referenced stereo line output from a single supply

line with minimal external components. The integrated DC servo eliminates the requirement for

external mute circuitry by minimising DC transients at the output during power up/down. The device

is well-suited to both stereo and multi-channel systems.

The device supports all common audio sampling rates between 8kHz and 192kHz using common

MCLK fs rates, with a slave mode audio interface.

The WM8524 supports a simple hardware control mode, allowing access to 24-bit LJ, RJ and I2S

audio interface formats, as well as a mute control. An internal audio interface clock monitor

automatically mutes the DAC output if the BCLK is interrupted.

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting audio data to the WM8524. The digital audio interface

uses three pins:



DACDAT: DAC data input

LRCLK: Left/Right data alignment clock

BCLK: Bit clock, for synchronisation

The WM8524 digital audio interface operates as a slave as shown in Figure 5.

Figure 5 Slave Mode

INTERFACE FORMATS

The WM8524 supports three different audio data formats:



Left justified

Right justified

I²S

All three of these modes are MSB first. They are described in Audio Data Formats on page 13. Refer

to the “Electrical Characteristics” section for timing information.

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WM8524

AUDIO DATA FORMATS

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 6 Right Justified Audio Interface (24-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 7 Left Justified Audio Interface (assuming n-bit word length)

In I²S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

PD, Rev 4.1, October 2011

WM8524

Production Data

Figure 8 I²S Justified Audio Interface (assuming n-bit word length)

DIGITAL AUDIO DATA SAMPLING RATES

The external master clock is applied directly to the MCLK input pin. In a system where there are a

number of possible sources for the reference clock, it is recommended that the clock source with the

lowest jitter be used for the master clock to optimise the performance of the WM8524.

The WM8524 has a detection circuit that automatically determines the relationship between the

master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock periods.

The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations

or jitter on the MCLK.

If during sample rate change the ratio between MCLK and LRCLK varies more than once within 1026

LRCLK periods, then it is recommended that the device be taken into the standby state or the off

state before the sample rate change and held in standby until the sample rate change is complete.

This will ensure correct operation of the detection circuit on the return to the enabled state. For details

on the standby state, please refer to the Power up and down control section of the datasheet on page

16.

The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz.

Table 3 shows typical master clock frequencies and sampling rates supported by the WM8524 DAC.

MASTER CLOCK FREQUENCY (MHz)

Sampling Rate

LRCLK

128fs

Unavailable

11.2896

192fs

Unavailable

16.9344

256fs

2.048

384fs

3.072

512fs

4.096

768fs

6.144

1152fs

9.216

8kHz

32kHz

8.192

12.288

16.384

24.576

36.864

44.1kHz

48kHz

11.2896

12.288

16.9344

18.432

22.5792

33.8688

Unavailable

24.576

36.864

88.2kHz

96kHz

22.5792

24.576

33.8688

36.864

Unavailable

12.288

18.432

176.4kHz

192kHz

22.5792

33.8688

Unavailable

24.576

36.864

Table 3 MCLK Frequencies and Audio Sample Rates

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WM8524

HARDWARE CONTROL INTERFACE

The device is configured according to logic levels applied to the hardware control pins as described in

Table 4.

PIN NAME

M¯¯U¯T¯E¯

NUMBER

DESCRIPTION

Mute Control

0 = Mute

1 = Normal operation

AIFMODE

Audio Interface Mode

0 = 24-bit LJ

1 = 24-bit I²S

Z = 24-bit RJ

Table 4 Hardware Control Pin Configuration

MUTE

The M¯¯U¯T¯E¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a

softmute is applied to ramp the signal down in 800 samples. When the mute is de-asserted the signal

returns to full scale in one step.

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POWER UP AND DOWN CONTROL

The MCLK, BCLK and M¯¯U¯T¯E¯ pins are monitored to control how the device powers up or down, and

this is summarised in Figure 9 below.

MCLK

Disabled

Off

MCLK Enabled

BCLK Enabled

MUTE=0

Standby

MCLK

Disabled

MCLK Enabled

BCLK Enabled

MUTE=1

BCLK

Disabled

BCLK Enabled

MUTE=1

MUTE=0

Enabled

Figure 9 Hardware Power Sequence Diagram

Off to Enable

To power up the device to enabled, start MCLK and BCLK and set M¯¯U¯T¯E¯ = 1.

Off to Standby

To power up the device to standby, start MCLK and BCLK and set M¯¯U¯T¯E¯ = 0. Once the

device is in standby mode, BCLK can be disabled and the device will remain in standby

mode.

Standby to Enable

To transition from the standby state to the enabled state, set the M¯¯U¯T¯E¯ pin to logic 1 and start BCLK.

Enable to Standby

To power down to a standby state leaving the charge pump running, either set the M¯¯U¯T¯E¯ pin to logic

0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute

and power down quietly in either case.

Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than

once in 1026 LRCLK periods, as detailed in Digital Audio Data Sampling Rates on page 14.

Enable to Off

To power down the device completely, stop MCLK at any time. It is recommended that the device is

placed into standby mode as described above before stopping MCLK to allow a quiet shutdown.

For the timing of the off state to enabled state transition (power on to audio out timing), and the

enabled state to standby state transition (the shutdown timing), please refer to WTN0302.

PD, Rev 4.1, October 2011

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WM8524

POWER DOMAINS

Supply Rail 2.97V … 3.63V

AVDD

LINEVDD

Device

Charge

Pump

Digital

Input Pins

Digital

Core

DAC L/R

DC Servo

Line Driver

LDO

POR

AGND

LINEGND

Ground Rail

Figure 10 Power Domain Diagram

POWER DOMAIN

NAME

BLOCKS USING

THIS DOMAIN

DOMAIN DESCRIPTION

DAC Power Supplies

3.3V ± 10%

AVDD

Line Driver

DAC

Analogue Supply

DC Servo

3.3V ± 10%

LINEVDD

Charge Pump

Digital LDO

Digital Pad buffers

Internally Generated Power Supplies and References

1.65V ± 10%

-3.3V ± 10%

VMID

DAC, LDO

Line Driver

Ext decoupled resistor string

CPVOUTN

Charge pump generated voltage

Table 5 Power Domains

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DIGITAL FILTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC Filter – 256fs to 1152fs

Passband

 0.1dB

f > 0.546fs

 0.1dB

0.454fs

0.1

Passband Ripple

Stopband

0.546fs

-50

Stopband attenuation

Group Delay

DAC Filter – 128fs and 192fs

Passband

0.247fs

0.1

Passband Ripple

Stopband

0.753fs

-50

Stopband attenuation

Group Delay

f > 0.753fs

TERMINOLOGY

1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)

2. Pass-band Ripple – any variation of the frequency response in the pass-band region

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WM8524

DAC FILTER RESPONSES

0.2

0.15

0.1

-20

0.05

-40

-60

-0.05

-0.1

-0.15

-0.2

-80

-100

-120

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)

0.5

1.5

2.5

Frequency (Fs)

Figure 11 DAC Digital Filter Frequency Response

– 256fs to 1152fs Clock Modes

Figure 12 DAC Digital Filter Ripple – 256fs to 1152fs Clock

Modes

0.2

-20

-0.2

-0.4

-0.6

-0.8

-1

-40

-60

-80

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

-100

Frequency (Fs)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequency (Fs)

Figure 13 DAC Digital Filter Frequency Response

– 128fs and 192fs Clock Modes

Figure 14 DAC Digital Filter Ripple – 128fs to 192fs Clock

Modes

PD, Rev 4.1, October 2011

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Production Data

APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

Figure 15 Recommended External Components

Notes:

1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to

optimize split ground configuration for audio performance.

2. Charge Pump fly-back capacitor C5 should be placed as close to WM8524 as possible, followed by Charge Pump

decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. See Recommended PCB Layout on p21.

3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum

performance.

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WM8524

RECOMMENDED ANALOGUE LOW PASS FILTER

Figure 16 Recommended Analogue Low Pass Filter (one channel shown)

An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other

filter architectures may provide equally good results.

The filter shown in Figure 16 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The

typical output from the WM8524 is 2.1Vrms – when a 10kΩ load is placed at the output of this

recommended filter the amplitude across this load is 1.99Vrms.

RECOMMENDED PCB LAYOUT

To LINEVDD

Supply

Top Layer Copper

Via

W M 8 5 2 4

To AVDD

Supply

Figure 17 Recommended PCB Layout

Notes:

1. C5 should be placed as close to WM8524 as possible, with minimal track lengths to reduce inductance and maximise

performance of the charge pump. Vias should be avoided in the tracking to C5.

2. C1 is then next most important and should also be placed as close as possible to the WM8524. Again, minimise track

lengths and avoid vias to reduce parasitic inductance.

3. C2 and C4 are then next most important, and lastly C3.

4. The WM8524 evaluation board, details available at www.wolfsonmicro.com, shows an example of good component

placement and layout to maximise performance with a minimal BOM.

PD, Rev 4.1, October 2011

WM8524

Production Data

RELEVANT APPLICATION NOTES

The following application notes, available from www.wolfsonmicro.com, may provide additional

guidance for use of the WM8524.

DEVICE PERFORMANCE:

WTN0302 – WM8524 Recommended Power Sequence and Timing

WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs

WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies

GENERAL:

WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging

WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention

WAN0158 – Lead-Free Solder Profiles for Lead-Free Components

WAN0161 – Electronic End-Product Design for ESD

PD, Rev 4.1, October 2011

Production Data

WM8524

PACKAGE DIMENSIONS

DT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm)

DM013.B

GAUGE

PLANE



0.25

-C-

0.1

SEATING PLANE

Dimensions

(mm)

NOM

-----

Symbols

MIN

MAX

1.20

0.15

1.05

0.30

0.20

5.10

A₁

A₂

E₁

-----

0.05

0.80

0.19

0.09

4.90

-----

1.00

-----

5.00

0.65 BSC

6.4 BSC

4.40

4.30

0.45

0^o

4.50

0.75

8^o

0.60

-----



REF:

JEDEC.95, MO-153

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.

D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

PD, Rev 4.1, October 2011

WM8524

Production Data

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,

delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the

right to make changes to its products and specifications or to discontinue any product or service without notice. Customers

should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating

safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer

product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for

such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where

malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other

intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or

services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document

belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is

accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is

not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in

this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or

accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any

reliance placed thereon by any person.

ADDRESS

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: apps@wolfsonmicro.com

PD, Rev 4.1, October 2011

Production Data

WM8524

REVISION HISTORY

DATE

REV

ORIGINATOR

CHANGES

25/10/11

4.1

JMacD

Order codes changed from WM8524GEDT and WM8524GEDT/R to

WM8524CGEDT and WM8524CGEDT/R to reflect change to copper wire

bonding.

PD, Rev 4.1, October 2011

WM8524CGEDT相关文章

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WM8524CGEDT产品参数

型号:	WM8524CGEDT
生命周期：	Transferred
IHS 制造商：	WOLFSON MICROELECTRONICS LTD
包装说明：	5 X 4.40 MM, 1 MM HEIGHT, LEAD FREE, MO-153AB, TSSOP-16
Reach Compliance Code：	unknown
风险等级：	5.74
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G16
长度：	5 mm
位数：	24
功能数量：	1
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
座面最大高度：	1.2 mm
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
宽度：	4.4 mm
Base Number Matches：	1

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