XC6132 Series
■OPERATIONAL DESCRIPTION (Continued)
②The VSEN pin voltage continues to drop, and when it reaches the detect voltage (VSEN=VDF), the Nch transistor for delay
capacitance discharge turns ON, and discharge of the delay capacitance Cd starts through the delay resistor Rn.
The time from VSEN=VDF until VRESETB reaches Low level is the detect delay time tDF (the detect time when the capacitor is not
connected to the Cd/MRB pin is tDF0). The delay capacitance Cd is discharged through the delay resistor Rn when it is above
the threshold voltage of VTCD2. When it is below the threshold voltage of VTCD2, the delay capacitance Cd is discharged faster
through the internal built-in low impedance switch.
③During the time that the VSEN pin voltage is below the detect voltage VDF, the delay capacitance Cd discharges to ground level.
The VSEN pin starts rising again, and during the time until it reaches the release voltage (VSEN<VDF+VHYS), VRESETB holds Low
level.
④The VSEN pin voltage continues to rise, and when it reaches the release voltage (VDF+VHYS), the Nch transistor for delay
capacitance discharge turns OFF, and charging of the delay capacitance Cd through the delay resistor Rp starts.The delay
capacitance Cd is discharged through the delay resistor Rp when it is below the threshold voltage of VTCD1. When it is above the
threshold voltage of VTCD1, the delay capacitance Cd is discharged faster through the internal built-in low impedance switch.
⑤When the delay capacitance pin voltage reaches VTCd1, VRESETB changes to High level.
The time from VSEN=VDF+VHYS until the VRESETB logic changes is the release delay time tDR(the release time when the capacitor
is not connected to the Cd/MRB pin is tDR0).
⑥During the time that the VSEN pin voltage is higher than the detect voltage (VSEN>VDF), VRESETB holds High level.
The above operation description is for an Active Low detection product.
For an Active High product, reverse the logic of the reset pin.
In the factory shipping state, internal hysteresis is not added (VHYS =VDFx0.001V(TYP.)), so please add a hysteresis of 1% or
more with an external resistor. For the calculation method, refer to <Hysteresis external adjustment function> below. Also
please refer to “Notes on use 5＆6” on page 19.
<Hysteresis external adjustment function>
Hysteresis can be added as desired by inserting a resistor between the node to monitor and VSEN pin, and between the VSEN pin
and HYS pin.
The calculation method for adding hysteresis by increasing only the release voltage and leaving the detect voltage unchanged
is given below.
For the circuit schematic, refer to Fig. 3: Hysteresis Augmentation Circuit 1.
VDR(H)=VDR(T)×{1+(RD/RE)}
Hysteresis width=VDR(H)-VDF(T)
Example 1: RD=200kΩ, RE=200kΩ, VDF(T)=1.000V, VDR(T)=1.001V.
VDR(H)=2.002V
Hysteresis width=2.002-1.000 =1.002V
The calculation method for detecting high voltage and adding hysteresis is shown below.
For the circuit schematic, refer to Fig. 4: Hysteresis Augmentation Circuit 2.
VDF(H)=VDF(T)×{1+(R1/R2)}
VDR(H)=VDR(T)×{1+(R1/R2)+(R1/R3)}
Hysteresis width=VDR(H)-VDF(H)
Example 2: R1=R3=500kΩ, R2=200kΩ, VDF(T)=2.000V, VDR(T)=2.002V.
VDF(H)=7.0V
VDR(H)=9.009V
Hysteresis width=9.009-7.0=2.009V
(Note 1) VDF(H) is the detect voltage after external adjustment.
(Note 2) VDR(H) is the release voltage after external adjustment.
(Note 3) VDR(T) is the release voltage.
(Note 4) VDF(T) is the detect voltage.
(Note 5) The R2 resistance is in parallel with the internal RSEN resistance, and thus to increase the accuracy of the detect
voltage and release voltage after external adjustment, select an R2 resistance that is sufficiently small with respect to the RSEN
resistance. For RSEN resistance values, refer to SPEC TABLE (p.11).
(Note 6) If high voltage is to be detected, divide the voltage with resistors R1 and R2 so that VSEN pin≦6V. The battery voltage
(+B) assumes up to 12V in this case.
+B
VDD
+B
VDD
R3
RE
VIN
VIN
R1
Rpull(*1)
RD
HYS
VSEN
HYS
VSEN
Rpull(*1)
RESET
RESETB
RESET
RESETB
R2
Cd/MRB
Cd/MRB
RESET
SW
Cd
RESET
SW
Cd
VSS
VSS
GND
GND
Fig. 3: Hysteresis Augmentation Circuit 1
Fig. 4: Hysteresis Augmentation Circuit 2
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