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产品型号XC95216-10PQ160I的概述

XC95216-10PQ160I的概述 XC95216-10PQ160I是一款由赛灵思（Xilinx）公司生产的可编程逻辑器件（PLD），属于其XC9500系列。该系列器件主要用于各种数字电路设计，包括但不限于数据处理、控制系统，以及其他一般信号处理应用。XC95216-10PQ160I作为该系列中的一员，具有特殊的特性和功能，适合多种嵌入式应用和工业控制。该器件的核心特征是它的内部架构，可以通过用户定义的逻辑来实现多种逻辑功能。XC95216-10PQ160I具备高效的逻辑单元配置和丰富的输入输出接口，为设计者提供了足够的灵活性以实现各种复杂的逻辑设计。其内部的并行处理能力确保了其高效性能，特别是在实时数据处理和反馈控制的应用场景中表现突出。芯片XC95216-10PQ160I的详细参数 XC95216-10PQ160I芯片的详细参数如下： - 逻辑单元数量：216个 - 最大输...

产品型号XC95216-10PQ160I的Datasheet PDF文件预览

XC95216 In-System Programmable

CPLD

August 21, 2001 (Version 3.1)

Product Specification

Features

Power Management

•

10 ns pin-to-pin logic delays on all pins

to 111 MHz

Power dissipation can be reduced in the XC95216 by con-

figuring macrocells to standard or low-power modes of

operation. Unused macrocells are turned off to minimize

power dissipation.

CNT

•

216 macrocells with 4800 usable gates

Up to 166 user I/O pins

5 V in-system programmable

Operating current for each design can be approximated for

specific operating conditions using the following equation:

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

(mA) =

•

Enhanced pin-locking architecture

Flexible 36V18 Function Block

(1.7) + MC (0.9) + MC (0.006 mA/MHz) f

HP LP

Where:

90 product terms drive any or all of 18 macrocells

within Function Block

= Macrocells in high-performance mode

Global and product term clocks, output enables, set

and reset signals

MC = Macrocells in low-power mode

MC = Total number of macrocells used

•

Extensive IEEE Std 1149.1 boundary-scan (JTAG)

support

= Clock frequency (MHz)

Programmable power reduction mode in each

macrocell

Slew rate control on individual outputs

User programmable ground pin capability

Extended pattern security features for design protection

High-drive 24 mA outputs

Figure 1 shows a typical calculation for the XC95216

device.

•

600

3.3 V or 5 V I/O capability

Advanced CMOS 5V FastFLASH technology

Supports parallel programming of more than one

XC9500 concurrently

(500)

400

(360)

•

Available in 160-pin PQFP, 352-pin BGA, and 208-pin

HQFP packages

(340)

Description

200

The XC95216 is a high-performance CPLD providing

advanced in-system programming and test capabilities for

general purpose logic integration. It is comprised of twelve

36V18 Function Blocks, providing 4,800 usable gates with

propagation delays of 10 ns. See Figure 2 for the architec-

ture overview.

100

Clock Frequency (MHz)

X5918

Figure 1: Typical I

vs. Frequency For XC95216

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

Macrocells

1 to 18

Function

Block 12

Macrocells

1 to 18

X5917

Figure 2: XC95216 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

Absolute Maximum Ratings

Symbol

Parameter

Value

Units

Supply voltage relative to GND

-0.5 to 7.0

DC input voltage relative to GND

-0.5 to V

+ 0.5

Voltage applied to 3-state output with respect to GND

Storage temperature

-0.5 to V

+ 0.5

-65 to +150

+260

°C

STG

SOL

Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under

Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods

of time may affect device reliability.

Recommended Operating Conditions

Symbol

Parameter

Min

Max

Units

Supply voltage for internal logic and input buffer

4.75

(4.5)

5.25

(5.5)

CCINT

Supply voltage for output drivers for 5 V operation

Supply voltage for output drivers for 3.3 V operation

Low-level input voltage

4.75 (4.5)

5.25 (5.5)

3.6

CCIO

3.0

0.80

High-level input voltage

Output voltage

2.0

+0.5

CCINT

CCIO

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics

Symbol

Parameter

Min

Max

Units

Years

Cycles

Data Retention

Program/Erase Cycles

10,000

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

Output high voltage for 5 V operation

= -4.0 mA

2.4

= Min

Output high voltage for 3.3 V operation

Output low voltage for 5 V operation

Output low voltage for 3.3 V operation

Input leakage current

= -3.2 mA

= Min

2.4

= 24 mA

0.5

0.4

= Min

= 10 mA

= Min

= Max

±10.0

10.0

µA

= GND or V

I/O high-Z leakage current

= Max

= GND or V

I/O capacitance

= GND

f = 1.0 MHz

Operating Supply Current

(low power mode, active)

V = GND, No load

f = 1.0 MHz

200 (typ)

AC Characteristics

XC95216-10 XC95216-15 XC95216-20

Symbol

Parameter

Units

Min

Max Min

Max

I/O to output valid

10.0

8.0

15.0

10.0

0.0

20.0

I/O setup time before GCK

I/O hold time after GCK

GCK to output valid

6.0

0.0

6.0

8.0

10.0

CNT

16-bit counter frequency

111.1

66.7

2.0

95.2

55.6

4.0

83.3

50.0

4.0

MHz

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock to output valid

GTS to output valid

SYSTEM

PSU

4.0

6.0

10.0

6.0

12.0

11.0

14.0

5.5

16.0

18.0

PCO

GTS to output disable

6.0

Product term OE to output enabled

Product term OE to output disabled

GCK pulse width (High or Low)

10.0

5.5

POE

POD

WLH

4.5

Note: 1. f_CNTis the fastest 16-bit counter frequency available, using the local feedback when applicable.

f_CNTis also the Export Control Maximum flip-flop toggle rate, f_TOG

2. f is the internal operating frequency for general purpose system designs spanning multiple FBs.

SYSTEM

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

TEST

Output Type

CCIO

TEST

Device Output

5.0 V

3.3 V

5.0 V

3.3 V

160 Ω

260 Ω

120 Ω

360 Ω

35 pF

X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

XC95216-10 XC95216-15 XC95216-20

Symbol

Parameter

Units

Min

Max Min

Max

Buffer Delays

Input buffer delay

3.5

2.5

6.0

3.0

0.0

4.5

3.0

6.5

3.0

GCK buffer delay

GSR buffer delay

GTS buffer delay

Output buffer delay

GCK

GSR

GTS

OUT

7.5

9.5

11.0

4.5

16.0

6.5

Output buffer enable/disable delay

0.0

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

3.0

2.5

3.5

2.5

3.0

5.0

2.5

3.0

5.0

PTCK

PTSR

PTTS

Internal Register and Combinatorial delays

Combinatorial logic propagation delay

1.0

3.5

3.0

3.5

4.0

PDI

SUI

2.5

3.5

4.5

6.5

Internal logic delay

0.5

8.0

COI

AOI

RAI

LOGI

7.0

10.0

2.5

8.0

10.0

3.0

t_LOGILP

Internal low power logic delay

11.0

11.5

Feedback Delays

FastCONNECT matrix feedback delay

Function Block local feeback delay

9.5

3.5

11.0

3.5

13.0

5.0

Time Adders

Incremental Product Term Allocator delay

Slew-rate limited delay

1.0

4.5

1.0

5.0

1.5

5.5

PTA

SLEW

Note: 3. t_PTAis multiplied by the span of the function as defined in the family data sheet.

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

XC95216 I/O Pins

Function

Block

BScan

Order

Function

Block

BScan

Order

Macrocell PQ160 HQ208 BG352

Notes

Macrocell PQ160 HQ208 BG352

Notes

–

645

642

639

636

633

630

627

624

621

618

615

612

609

606

603

600

597

594

591

588

585

582

579

576

573

570

567

564

561

558

555

552

549

546

543

540

–

537

534

531

528

525

522

519

516

513

510

507

504

501

498

495

492

489

486

483

480

477

474

471

468

465

462

459

456

453

450

447

444

441

438

435

432

M25

M26

N26

N25

P23

–

AA26

Y24

U23

AB25

AA24

–

[1]

–

P24

R26

G26

R24

T26

–

Y23

AA23

AD18

AB24

AD25

–

T25

T23

V26

U24

–

AD23

AF24

AE12

AE23

–

[1]

–

E25

G24

P25

F26

H23

–

[1]

152

153

–

198

199

196

200

201

–

D18

A21

B19

B20

C20

–

154

155

–

K23

K24

–

156

158

–

202

205

B22

B24

–

J25

L24

–

159

206

C23

E23

–

[1]

–

K25

L26

H25

M24

–

C26

E24

D20

F24

–

[1]

–

203

–

Note: 1. Global control pin.

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

XC95216 I/O Pins (continued)

Function

BScan

Order

Function

BScan

Order

Macrocell PQ160 HQ208 BG352

Block

Notes

Macrocell PQ160 HQ208 BG352

Notes

Block

–

429

426

423

420

417

414

411

408

405

402

399

396

393

390

387

384

381

378

375

372

369

366

363

360

357

354

351

348

345

342

339

336

333

330

327

324

–

AE13

AC13

AE24

AD13

AD12

–

321

318

315

312

309

306

303

300

297

294

291

288

285

282

279

276

273

270

267

264

261

258

255

252

249

246

243

240

237

234

231

228

225

222

219

216

AE22

AE21

W25

AF21

AD19

–

AE20

AF18

AD1

AE17

AE16

–

AC12

AF11

AD8

AE11

AE9

–

109

–

AF16

AE14

Y26

AF14

–

AD9

AC10

AC26

AF7

–

140

142

–

180

182

208

185

186

–

A12

A13

D22

C14

A15

–

126

128

–

162

164

143

166

167

–

143

144

–

129

130

–

145

146

–

187

188

183

191

192

–

B15

C15

B14

A16

C16

–

131

132

–

170

171

195

173

174

–

C10

A20

D11

–

147

148

–

133

134

–

149

150

–

193

194

169

197

–

C17

B18

135

138

–

175

178

189

179

–

B11

C12

D15

B12

–

151

–

C19

–

139

–

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

XC95216 I/O Pins (continued)

Function

Block

BScan

Order

Function

Block

BScan

Order

Macrocell PQ160 HQ208 BG352

Notes

Macrocell PQ160 HQ208 BG352

Notes

–

AD7

AE5

AD4

AC7

AE3

–

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

–

105

102

115

116

119

117

118

–

101

100

–

102

103

AC5

AD3

AE8

AA4

AB2

–

121

122

107

123

125

–

AC3

–

110

111

–

112

113

AC1

AA2

AC19

AA1

–

126

127

120

128

–

114

–

113

114

–

147

148

144

149

150

–

101

102

–

131

133

106

134

135

–

AD2

–

115

116

–

103

104

–

117

118

–

152

154

168

155

158

–

105

106

–

136

137

151

138

139

–

119

122

–

107

108

–

123

124

–

159

160

165

161

–

109

111

–

140

145

142

146

–

125

–

112

–

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

XC95216 Global, JTAG and Power Pins

Pin Type

PQ160

HQ208

BG352

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GTS3

I/O/GTS4

I/O/GSR

TCK

Y24

AA24

AD23

E25

F26

E23

E24

159

206

C23

AD6

TDI

TDO

136

176

AF6

D12

AE6

TMS

5 V

10,46,94,157

1,41,61,81,121,141

11, 59, 124, 153, 204

1, 26, 53, 65, 79, 92, 105, 132,

157, 172, 181, 184

H24, AF23, T1, G4, C22

CCINT

3.3 V/5 V

A10, A17, B2, B25, D7, D13,

D19, G23, H4, K1, K26, N23, P4,

U1, U26, W23, Y4, AC8, AC14,

AC20, AE25, AF10, AF17

CCIO

GND

20, 31, 40, 51, 70, 80, 99, 100, 2, 13, 24, 27, 42, 52, 66, 68, 69, A1, A2, A5, A8, A14, A19, A22,

110, 120, 127, 137, 160

81, 93, 104, 108, 129, 130, 141, A25, A26, B1, B26, C7, E1, E26,

156, 163, 177, 190, 207

H1, H26, N1, P3, P26, V23, W1,

W26, AB1, AB4, AB26, AC9,

AC17, AE1, AE26, AF1, AF2,

AF5, AF8, AF13, AF19, AF20,

AF22, AF25, AF26

No Connects

–

A4, A11, A18, A23, A24, B4, B8,

B10, B13, B16, B17, B21, B23,

C1, C2, C3, C4, C5, C8, C9, C11,

C13, C18, C21, C24, C25, D1,

D3, D4, D5, D10, D14, D16, D17,

D21, D23, D24, D25, D26, E3,

E4, F1, F3, F23, F25, G25, J2,

J3, J23, J24, J26, K2, K4, L4,

L23, L25, M2, M23, N24, P2,

R23, R25, T3, T4, T24, U25, V1,

V24, V25, W3, W4, W24, Y2, Y3,

Y25, AA3, AA25, AB3, AB23,

AC2, AC4, AC6, AC11, AC15,

AC16, AC18, AC21, AC22,

AC23, AC24, AC25, AD5, AD10,

AD11, AD14, AD15, AD16,

AD17, AD20, AD21, AD22,

AD24, AD26, AE2, AE4, AE7,

AE10, AE15, AE18, AE19, AF3,

AF4, AF9, AF12, AF15

August 21, 2001 (Version 3.1)

XC95216 In-System Programmable CPLD

Ordering Information

XC95216 -10 HQ 208 C

Device Type

Speed

Temperature Range

Number of Pins

Package Type

Speed Options

- 20 20 ns pin-to-pin delay

Packaging Options

PQ160 160-Pin Plastic Quad Flat Pack (PQFP)

HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP)

BG352 352-Pin Ball Grid Array (BGA)

-15 15 ns pin-to-pin delay

-10 10 ns pin-to-pin delay

Temperature Options

Commercial 0°C to +70°C

Industrial –40°C to +85°C

Component Availability

Pins

Type

Code

160

208

352

Plastic

PQFP

Plastic

BGA

Power QFP

PQ160

C(I)

HQ208

C(I)

BG352

C(I)

–20

–15

–10

XC95216

C(I)

C = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C

Revision Control

Date

Revision

Update AC Characteristics and Internal Parameters

Added Note 1 to page 6.

12/4/98

8/21/01

August 21, 2001 (Version 3.1)

XC95216-10PQ160I相关文章

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XC95216-10PQ160I产品参数

型号:	XC95216-10PQ160I
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	PLASTIC, QFP-160
针数：	160
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.81
其他特性：	216 MACROCELLS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
最大时钟频率：	66.7 MHz
系统内可编程：	YES
JESD-30 代码：	S-PQFP-G160
JESD-609代码：	e0
JTAG BST：	YES
长度：	28 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	133
宏单元数：	216
端子数量：	160
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 133 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装等效代码：	QFP160,1.2SQ
封装形状：	SQUARE
封装形式：	FLATPACK
峰值回流温度（摄氏度）：	225
电源：	3.3/5,5 V
可编程逻辑类型：	FLASH PLD
传播延迟：	10 ns
认证状态：	Not Qualified
座面最大高度：	3.7 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	28 mm
Base Number Matches：	1

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