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产品型号XPC8240RZU250E的概述

XPC8240RZU250E芯片概述 XPC8240RZU250E是由Freescale Semiconductor（现为NXP Semiconductors）推出的高性能嵌入式微处理器，属于PowerQUICC系列中的一员。这款芯片广泛应用于网络设备、通信系统和工业控制等领域，其设计旨在提升数据处理能力和网络通信性能。XPC8240RZU250E的核心基于PowerPC架构，具备强大的处理能力和灵活的外设接口，适合多种嵌入式应用。详细参数 XPC8240RZU250E的技术规格如下： - 处理器核心：PowerPC 603e - 时钟频率：250 MHz - 数据总线宽度：32位 - 地址总线宽度：32位 - 数据缓存：32KB L1 Cache（指令）和32KB L1 Cache（数据） - 外部内存支持：SDRAM、EDO DRAM、FIFO等 - 集成外设：支持多种通信接口，...

产品型号XPC8240RZU250E的Datasheet PDF文件预览

Freescale Semiconductor, Inc.

Advance Information

MPC8240RXXPNS

Rev. 0, 11/2003

MPC8240 Part Number

Specification for the

XPC8240RXXnnnx Series

Part

This document describes part-number-specific changes to recommended operating conditions

and revised electrical specifications, as applicable, from those described in the general

MPC8240 Integrated Processor Hardware Specifications (Order No. MPC8240EC).

Numbers Affected:

XPC8240RZU250E

XPC8240RVV250E

Specifications provided in this document supersede those in the MPC8240 Integrated

Processor Hardware Specifications, Revision 1.0 or later, for the part numbers listed in

Table A only. Specifications not addressed herein are unchanged. Because this document is

frequently updated, refer to http://www.freescale.com or to a local Freescale

sales office for the latest version.

Note that headings and table numbers in this document are not consecutively numbered. They

correspond to the heading or table affected in the general hardware specification.

The part numbers addressed in this document are listed in Table A. For more detailed ordering

information, see Section 1.9, “Ordering Information.”

Table A. Part Number Addressed by This Data Sheet

Operating Conditions

Significant Differences from

Hardware Specification

Part Number

CPU

Frequency

V_DD

T_J(°C)

XPC8240RVV250x

XPC8240RZU250x

250 MHz

2.625 ±125 mV 0 to 105 Modified voltage specifications to

achieve 250 MHz

Note: The X prefix in a Freescale part number designates a “Pilot Production Prototype” as defined by

Freescale SOP 3-13. These are part of a limited production volume of prototypes manufactured, tested,

and Q.A.-inspected on qualified technology to simulate normal production. These parts have only

preliminary reliability and characterization data. Before pilot production prototypes may be shipped,

written authorization from the customer must be on file in the applicable sales office acknowledging the

qualification status and the fact that product changes may still occur while shipping pilot production

prototypes.

1.2 Features

This section summarizes changes to the features of the MPC8240 described in the MPC8240

Integrated Processor Hardware Specifications.

•

Power management

For More Information On This Product,

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General Parameters

— 2.625-V processor core

1.3 General Parameters

This section summarizes changes to the general parameters of the MPC8240 described in the MPC8240

Integrated Processor Hardware Specifications.

•

Core power supply 2.625 V ±125 mV DC nominal

1.4.1. DC Electrical Characteristics

Table 2 provides the recommended operating conditions for the MPC8240 part numbers described herein.

Table 2. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit

Notes

Value

Supply voltage

V_DD

2.625 ±5%

3.3 ±0.3

4, 6

Supply voltage for PCI and standard bus standards

Supply voltages for memory bus drivers

PLL supply voltage—CPU core logic

PLL supply voltage—peripheral logic

DLL supply voltage

OV_DD

GV_DD

AV_DD

3.3 ±5%

2.625 ±5%

2.6255 ±5%

2.625 ±5%

5.0 ±5%

4, 6

4, 7

9, 10

2, 3

AV_DD

LAV_DD

LV_DD

PCI reference

3.3 ±0.3

Input voltage

LV_DDinput-tolerant signals

All other inputs

V_in

0 to 3.6 or 5.75

0 to 3.6

MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Parameters

Table 2. Recommended Operating Conditions (continued)

Recommended

Characteristic

Symbol

Unit

Notes

Value

Die-junction temperature

Notes:

T_j

0 to 105

°C

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

2. These signals are designed to withstand LV_DD+ 0.5 V DC when LV_DDis connected to a 3.3- or 5.0-V DC power

supply.

3. LV_DDinput tolerant signals: PCI interface, EPIC control, and OSC_IN signals.

4. See Section 1.9, “Ordering Information,” for details on a modified voltage (V_DD) version device.

Cautions:

5. Input voltage (V_in) must not be greater than the supply voltage (V_DD/AV_DD/AV_DD2/LAV_DD) by more than 2.5 V at all

times, including during power-on reset.

6. OV_DDmust not exceed V_DD/AV_DD/AV_DD2/LAV_DDby more than 1.8 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

7. V_DD/AV_DD/AV_DD2/LAV_DDmust not exceed OV_DDby more than 0.6 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. GV_DDmust not exceed V_DD/AV_DD/AV_DD2/LAV_DDby more than 1.8 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

9. LV_DDmust not exceed V_DD/AV_DD/AV_DD2/LAV_DDby more than 5.4 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

10.LV_DDmust not exceed OV_DDby more than 3.6 V at any time, including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

1.4.1.5 Power Characteristics

Table 5 provides power consumption data for the MPC8240. Power consumption on the PLL supply pins (AV_DD

and AV_DD2) and the DLL supply pin (LAVDD) less than 15 mW. This parameter is guaranteed by design and is not

tested.

Table 5. Preliminary Power Consumption

PCI Bus Clock/Memory Bus Clock

CPU Clock Frequency (MHz)

Mode

Unit Notes

33/66/233

33/83/250 33/100/200 33/100/250 66/100/200 66/100/250

Typical

3.4

3.8

3.4

2.2

700

500

3.6

4.1

3.7

2.4

800

500

3.2

3.6

3.3

2.2

900

500

3.7

4.2

3.8

2.6

900

500

3.2

3.6

3.4

2.2

900

800

3.8

4.3

3.8

2.6

900

800

1, 5

1, 2

Maximum—FP

Maximum—INT

Doze

1, 3

1, 4, 6

Nap

mW 1, 4, 6

Sleep

I/O Power Supplies

Mode

Minimum

Maximum

Unit Notes

Typical—OV_DD

200

600

7, 8

MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

For More Information On This Product,

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Freescale Semiconductor, Inc.

PLL Configurations

Table 5. Preliminary Power Consumption (continued)

PCI Bus Clock/Memory Bus Clock

CPU Clock Frequency (MHz)

Mode

Unit Notes

33/66/233

33/83/250 33/100/200 33/100/250 66/100/200 66/100/250

300 900

Typical—GV_DD

7, 9

Notes:

1. The values include V_DD, AV_DD, AV_DD2, and LAV_DDbut do not include I/O supply power; see Section 1.7.2, “Power

Supply Sizing,” in the MPC8240 Integrated Processor Hardware Specifications for information on OV_DDand GV_DD

supply power. One DIMM is used for memory loading.

2. Maximum—FP power is measured at V_DD= 2.625 V with dynamic power management enabled while running an

entirely cache-resident, looping, floating point multiplication instruction.

3. Maximum—INT power is measured at V_DD= 2.625 V with dynamic power management enabled while running

entirely cache-resident, looping, integer instructions.

4. Power saving mode maximums are measured at V_DD= 2.625 V while the device is in doze, nap, or sleep mode.

5. Typical power is measured at V_DD= AV_DD= 2.625 V, OV_DD= 3.3 V where a nominal FP value, a nominal INT value,

and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries

to local memory are averaged.

6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.

7. The typical minimum I/O power values were results of the MPC8240 performing cache resident integer operations

at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.

8. The typical maximum OV_DDvalue resulted from the MPC8240 operating at the fastest frequency combination of

66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and

zeros to PCI memory.

9. The typical maximum GV_DDvalue resulted from the MPC8240 operating at the fastest frequency combination of

66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and

zeros on 64-bit boundaries to local memory.

1.5 PLL Configurations

The MPC8240 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN

(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)

frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)

frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the

MPC8240 is shown in Table 18.

Table 18. MPC8240 Microprocessor PLL Configurations

250-MHz Part ^{8, 9}

Ratios ^{3, 4}

PLL_

CFG

Ref.

No.

CPU ¹

HID1[0:4]

Peripheral

Logic/Mem

Bus Clock Range

(MHz)

PCIClockInput

(PCI_SYNC_IN)

Range (MHz)

CPU Clock

Range

PCI to Mem

(Mem VCO)

Multiplier

Mem to CPU

(CPU VCO)

Multiplier

[0:4] ²

(MHz)

00000

00001

00010

00011

00100

00110

11000

00101

25–33

25–27

75–100

75–83

188–250

225–250

100–112

3 (6)

2.5 (5)

3 (6)

2 (8)

50–56 ⁵

50–56

1 (4)

Bypass

50–56

Bypass

2 (8)

25–28 ⁵

100–113

MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

For More Information On This Product,

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Freescale Semiconductor, Inc.

Ordering Information

Table 18. MPC8240 Microprocessor PLL Configurations (continued)

250-MHz Part ^{8, 9}

Ratios ^{3, 4}

PLL_

CFG

Ref.

No.

CPU ¹

HID1[0:4]

Peripheral

Logic/Mem

Bus Clock Range

(MHz)

PCIClockInput

(PCI_SYNC_IN)

Range (MHz)

CPU Clock

Range

PCI to Mem

(Mem VCO)

Multiplier

Mem to CPU

(CPU VCO)

Multiplier

[0:4] ²

(MHz)

00101

00111

01000

01010

01100

01110

10000

10010

10100

10110

11000

11010

11100

11101

11110

11111

00110

11000

00111

00110

11000

00100

11110

11010

11000

11010

11000

00110

01111

11111

Bypass

33–56

50–55

50–100

50–83

75–100

50–100

50–71

50–62

62–83

50–62

50–83

50–100

Bypass

1 (4)

2.5 (5)

3 (6)

4.5 (9)

2.5 (5)

3 (6)

2 (4)

3.5 (7)

4 (8)

3 (6)

4 (8)

3 (6)

2.5 (5)

Off

33 ⁶–56 ⁵

25–27

100–168

225–250

125–250

150–250

150–200

100–200

175–250

200–250

186–250

200–250

150–250

125–250

2 (4)

25–50

2 (4)

25–41

2 (4)

25–33

3 (6)

33–66

1.5 (3)

2 (4)

25–35

25–31

2 (4)

25–33

2.5 (5)

1 (2)

50 ⁷–62

33 ⁷–55

33 ⁷–66

1.5 (3)

Off

Not usable

Off

Notes:

1. The processor HID1 values only represent the multiplier of the processor’s PLL (memory-to-processor multiplier);

thus, multiple MPC8240 PLL_CFG[0:4] values may have the same processor HID1 value. This implies that system

software cannot read the HID1 register and associate it with a unique PLL_CFG[0:4] value.

2. PLL_CFG[0:4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and

11011) are reserved.

3. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL

is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling

support. The AC timing specifications given in this document do not apply in PLL bypass mode.

4. In clock-off mode, no clocking occurs inside the MPC8240 regardless of the PCI_SYNC_IN input.

5. Limited due to maximum memory VCO = 225 MHz.

6. Limited due to minimum CPU VCO = 200 MHz.

7. Limited due to minimum memory VCO = 100 MHz.

8. For clarity, range values are shown rounded down to the nearest whole number (decimal place accuracy removed).

9. Note that the 250-MHz part is available only in the XPC8240RZUnnnx number series.

1.9 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in Section 1.9.1,

“Part Numbers Fully Addressed by This Document.”

MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

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Document Revision History

1.9.1 Part Numbers Fully Addressed by This Document

Table 19 provides the Freescale part numbering nomenclature for the MPC8240. Note that the individual

part numbers correspond to the maximum processor core frequency. For available frequencies, contact a

local Freescale sales office. Each part number also contains a revision code that refers to the die mask

revision number. The revision level can be determined by reading the Revision ID register at address offset

0x08.

Table 19. Freescale Part Numbering Nomenclature

XPC

nnnn

nnn

Processor

Frequency

Product Code

Part Identifier

Process Descriptor

Package

Revision Level

XPC

8240

R=2.625 V ±125 mV ZU = TBGA

0° to 105°C V V = Lead free

TBGA

E: 1.3;

Revision ID = 0x13

250

1.9.2 Part Marking

Parts are marked as in the example shown in Figure 28.

XPC8240R

XX250E

MMMMMM

ATWLYYWWA

8240

TBGA

Notes:

MMMMMM is the 6-digit mask number.

ATWLYYWWA is the traceability code.

Figure 28. Freescale Part Marking for TBGA Device

Document Revision History

Table B provides a revision history for this part number specification.

Table B. Document Revision History

Revision Number

Substantive Change(s)

Initial release. Note that this document supercedes the MPC8245RZUPNS.

MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

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Document Revision History

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MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

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XPC8240RZU250E产品参数

型号:	XPC8240RZU250E
生命周期：	Transferred
零件包装代码：	BGA
包装说明：	LBGA, BGA352,26X26,50
针数：	352
Reach Compliance Code：	unknown
ECCN代码：	3A001.A.3
HTS代码：	8542.31.00.01
风险等级：	5.61
Is Samacsys：	N
其他特性：	ALSO REQUIRES 3.3V I/O SUPPLY
地址总线宽度：	32
位大小：	32
边界扫描：	YES
最大时钟频率：	66 MHz
外部数据总线宽度：	64
格式：	FLOATING POINT
集成缓存：	YES
JESD-30 代码：	S-PBGA-B352
长度：	35 mm
低功率模式：	YES
端子数量：	352
封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA
封装等效代码：	BGA352,26X26,50
封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5,3.3 V
认证状态：	Not Qualified
座面最大高度：	1.65 mm
速度：	250 MHz
子类别：	Microprocessors
最大供电电压：	2.625 V
最小供电电压：	2.375 V
标称供电电压：	2.5 V
表面贴装：	YES
技术：	CMOS
端子形式：	BALL
端子节距：	1.27 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	35 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC
Base Number Matches：	1

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