can be combined with frequency and voltage to represent
active power dissipation.
E quiv al ent C apac it ance
where:
m
n
p
q
1
q
2
= Number of logic modules switching at f
m
= Number of input buffers switching at f
n
= Number of output buffers switching at f
p
= Number of clock loads on the first routed
array clock (all families)
= Number of clock loads on the second routed
array clock (ACT 2, 1200XL, 3200DX, ACT 3
only)
= Fixed capacitance due to first routed array
clock (all families)
= Fixed capacitance due to second routed array
clock (ACT 2, 1200XL, 3200DX, ACT 3 only)
= Fixed number of clock loads on the dedicated
array clock (ACT 3 only)
= Fixed number of clock loads on the dedicated
I/O clock (ACT 3 only)
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers
in pF
= Equivalent capacitance of routed array clock
in pF
= Equivalent capacitance of dedicated array
clock in pF
= Equivalent capacitance of dedicated I/O clock
in pF
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
(all families)
= Average second routed array clock rate in
MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)
= Average dedicated array clock rate in MHz
(ACT 3 only)
= Average dedicated I/O clock rate in MHz
(ACT 3 only)
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
Power (uW) = C
EQ
* V
CC2
* F
where:
C
EQ
V
CC
F
= Equivalent capacitance in pF
= Power supply in volts (V)
= Switching frequency in MHz
(1)
r
1
r
2
s
1
s
2
C
EQM
C
EQI
C
EQO
C
EQCR
C
EQCD
Equivalent capacitance is calculated by measuring I
CC
active
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a range
of frequencies at a fixed value of V
CC
. Equivalent capacitance
is frequency independent so that the results can be used over
a wide range of operating conditions. Equivalent capacitance
values are shown below.
CE Q Val ues f or Act el FP G A s
1200XL
ACT 3 3200DX ACT 2 ACT 1
Modules (C
EQM
)
Input Buffers (C
EQI
)
Output Buffers (C
EQO
)
Routed Array Clock
Buffer Loads (C
EQCR
)
Dedicated Clock Buffer
Loads (C
EQCD
)
I/O Clock Buffer Loads
(C
EQCI
)
6.7
7.2
10.4
1.6
0.7
0.9
5.2
11.6
23.8
3.5
N/A
N/A
5.8
12.9
23.8
3.9
N/A
N/A
3.7
22.1
31.2
4.6
C
EQCI
N/A
C
L
N/A
f
m
f
n
f
p
f
q1
f
q2
f
s1
f
s2
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piecewise linear summation
over all components that applies to all ACT 1, 1200XL,
3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has
only one routed array clock, the terms labeled routed_Clk2,
dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2
family has two routed array clocks, and the dedicated_Clk
and IO_Clk terms do not apply. For ACT 3 devices, all terms
will apply.
Power = V
CC2
* [(m * C
EQM
* f
m
)
modules
+ (n * C
EQI
* f
n
)
inputs
+
(p * (C
EQO
+ C
L
) * f
p
)
outputs
+ 0.5 * (q
1
* C
EQCR
* f
q1
)
routed_Clk1
+ (r
1
* f
q1
)
routed_Clk1
+ 0.5 * (q
2
* C
EQCR
* f
q2
)
routed_Clk2
+
(r
2
* f
q2
)
routed_Clk2
+ 0.5 * (s
1
* C
EQCD
* f
s1
)
dedicated_Clk
+
(s
2
* C
EQCI
* f
s2
)
IO_Clk
]
(2)
12
ACTEL [ Actel Corporation ]
