ProASIC3 Device Family Overview
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages
(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended
and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these
banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
•
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Part Number and Revision Date
Part Number 51700097-001-1
Revised February 2008
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
51700097-001-1
Changes in Current Version (v1.0)
This document was divided into two sections and given a version number,
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The second
section is a device family overview.
This document was updated to include A3P015 device information. QN68 is a
new package that was added because it is offered in the A3P015. The following
sections were updated:
note
"Introduction and Overview"
The
table is new.
In the
the QN package measurements were
updated to include both 0.4 mm and 0.5 mm.
In the
the number of I/Os was updated from 288
to 300.
v2.2
(July 2007)
This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel has restarted the version numbers. The new version
number is 51700097-001-0.
II
N/A
N/A
Page
51700097-001-0
(January 2008)
v1.0
1-7
ACTEL [ Actel Corporation ]
