Axcelerator Family FPGAs
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel’s back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the SmartGen core generator, which easily
creates popular and commonly used logic functions for
implementation into your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
In-System Diagnostic and Debug
Capabilities
The Axcelerator family of FPGAs includes internal probe
circuitry, allowing the designer to dynamically observe
and analyze any signal inside the FPGA without disturbing
normal device operation. Up to four individual signals can
be brought out to dedicated probe pins (PRA/B/C/D) on
the device. The probe circuitry is accessed and controlled
via Silicon Explorer II (Figure
Actel's integrated
verification and logic analysis tool that attaches to the
serial port of a PC and communicates with the FPGA via
the JTAG port (See
Summary
Programming
Programming support is provided through Actel's Silicon
Sculptor II, a single-site programmer driven via a PC-
based GUI. In addition, BP Microsystems offers multi-site
programmers that provide qualified support for Actel
devices. Factory programming is available for high-
volume production needs.
Actel’s Axcelerator family of FPGAs extends the
successful SX-A architecture, adding embedded RAM/
FIFOs, PLLs, and high-speed I/Os. With the support of a
suite of robust software tools, design engineers can
incorporate high gate counts and fixed pins into an
Axcelerator design yet still achieve high performance
and efficient device utilization.
16 Pin
Connection
TDI
TCK
Axcelerator FPGAs
Serial
Connection
Silicon Explorer II
TMS
TDO
PRA
PRB
22 Pin
Connection
CH3/PRC
CH4/PRD
Additional 14 Channels
(Logic Analyzer)
Figure 1-9 •
Probe Setup
v2.7
1-7
ACTEL [ Actel Corporation ]
