eX Family FPGAs
eX Family FPGAs
General Description
The eX family of FPGAs is a low-cost solution for low-
power, high-performance designs. The inherent low
power attributes of the antifuse technology, coupled
with an additional low static power mode, make these
devices ideal for power-sensitive applications. Fabricated
with an advanced 0.22µm CMOS antifuse technology,
these devices achieve high performance with no power
penalty
.
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure
The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hard-wired clock or
the routed clock.
The C-cell implements a range of combinatorial functions
up to five inputs (Figure
Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing non-timing-
critical paths and when the design engineer is running
out of R-cells. More information about the CC macro can
be found in Actel’s
application
note.
eX Family Architecture
Actel's eX family is implemented on a high-voltage twin-
well CMOS process using 0.22µm design rules. The eX
family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented
metal-to-metal
programmable
antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25Ω with a capacitance of 1.0fF for
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
S0
Routed
Data Input S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CKS
Figure 1-1 •
R-Cell
CLR
CKP
v4.3
1-1
ACTEL [ Actel Corporation ]
