PLUS
ProASIC
Flash Family FPGAs
Table 1-35 • Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
1
2
Max. tINYH
Max. tINYL
Std.
Macro Type
IB33
Description
Std.
0.5
Units
ns
3.3V, CMOS Input Levels3, No Pull-up Resistor
0.6
IB33S
3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
0.6
0.8
ns
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3V for delays.
Table 1-36 • Worst-Case Military Conditions
VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
1
2
Max. tINYH
Std.
Max. tINYL
Std.
Macro Type
IB25LP
Description
Units
ns
2.5V, CMOS Input Levels3, Low Power
0.9
0.7
IB25LPS
2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger
0.8
1.0
ns
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3V for delays.
v5.2
1-47
ACTEL [ Actel Corporation ]
