ProASIC
PLUS
Flash Family FPGAs
Predicted Global Routing Delay
Table 1-41 •
Worst-Case Commercial Conditions
1
V
DDP
= 3.0 V, V
DD
= 2.3 V, T
J
= 70°C
Max.
Parameter
t
RCKH
t
RCKL
t
RCKH
t
RCKL
Notes:
1.
2.
3.
4.
The timing delay difference between tile locations is less than 15ps.
All –F parts are only available as commercial.
Highly loaded row 50%.
Minimally loaded row.
Input Low to High
3
Input High to Low
3
Input Low to High
4
Input High to Low
4
Description
Std.
1.1
1.0
0.8
0.8
–F
2
1.3
1.2
1.0
1.0
Units
ns
ns
ns
ns
Table 1-42 •
Worst-Case Military Conditions
V
DDP
= 3.0V, V
DD
= 2.3V, T
J
= 125°C for Military/MIL-STD-883
Parameter
t
RCKH
t
RCKL
t
RCKH
t
RCKL
Description
Input Low to High (high loaded row of 50%)
Input High to Low (high loaded row of 50%)
Input Low to High (minimally loaded row)
Input High to Low (minimally loaded row)
Max.
1.1
1.0
0.8
0.8
Units
ns
ns
ns
ns
Note:
* The timing delay difference between tile locations is less than 15 ps.
Global Routing Skew
Table 1-43 •
Worst-Case Commercial Conditions
V
DDP
= 3.0 V, V
DD
= 2.3 V, T
J
= 70°C
Max.
Parameter
t
RCKSWH
t
RCKSHH
Description
Maximum Skew Low to High
Maximum Skew High to Low
Std.
270
270
–F*
320
320
Units
ps
ps
Note:
*All –F parts are only available as commercial.
Table 1-44 •
Worst-Case Commercial Conditions
V
DDP
= 3.0V, V
DD
= 2.3V, T
J
= 125°C for Military/MIL-STD-883
Parameter
t
RCKSWH
t
RCKSHH
Description
Maximum Skew Low to High
Maximum Skew High to Low
Max.
270
270
Units
ps
ps
1 -5 0
v5.2
ACTEL [ Actel Corporation ]
