PLUS
ProASIC
Flash Family FPGAs
Module Delays
A
B
C
Y
50%50%
A
B
50%50%
C
Y
50%50%
50%
50%
50%
50%
50%
tDBLH
50%
tDCHL
tDCLH
tDBHL
tDAHL
tDALH
Figure 1-29 • Module Delays
Sample Macrocell Library Listing
Table 1-45 • Worst-Case Military Conditions1
VDD = 2.3 V, TJ = 70º C, TJ = 70°C, TJ = 125°C for Military/MIL-STD-883
Std.
–F2
Cell Name
NAND2
AND2
Description
Max
Min
Max
0.6
0.8
1.0
0.6
1.0
0.8
Min
Units
ns
2-Input NAND
2-Input AND
3-Input NOR
0.5
0.7
0.8
0.5
0.8
0.6
ns
NOR3
ns
MUX2L
OA21
2-1 MUX with Active Low Select
2-Input OR into a 2-Input AND
2-Input Exclusive OR
ns
ns
XOR2
ns
LDL
Active Low Latch (LH/HL)
ns
LH3
HL3
0.9
0.8
1.1
0.9
CLK-Q
ns
ns
ns
ns
tsetup
0.7
0.1
0.8
0.2
thold
DFFL
Negative Edge-Triggered D-type Flip-Flop (LH/HL)
LH3
HL3
0.9
0.8
1.1
1.0
CLK-Q
ns
ns
ns
tsetup
thold
0.6
0.0
0.7
0.0
Notes:
1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of
local interconnect.
2. All –F parts are only available as commercial.
3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.
v5.2
1-51
ACTEL [ Actel Corporation ]
