PLUS
ProASIC
Flash Family FPGAs
Table 1-48 • JTAG Switching Characteristics
Description
Symbol
tTCKTDI
tTDOTCK
tTCKTDO
tTCK
Min
–4
Max
Unit
ns
Output delay from TCK falling to TDI, TMS
TDO Setup time before TCK rising
TDO Hold time after TCK rising
TCK period
4
10
ns
0
ns
100 2
1,000
1,000
ns
RCK period
tRCK
100
ns
Notes:
1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 1-21 on page 1-36 when VDDP = 2.5 V
and Table 1-22 on page 1-38 when VDDP = 3.3 V.
2. If RCK is being used, there is no minimum on the TCK period.
TCK
tTCK
TMS, TDI
tTCKTDI
TDO
tTDOTCK
tTCKTDO
Figure 1-30 • JTAG Operation Timing
v5.2
1-53
ACTEL [ Actel Corporation ]
