AD7886
PIN CONFIGURATIONS
PLCC
DIP
1
2
28
DB8
27 DB9
DB10
DB7
DB6
4
2
1
28 27 26
3
3
DB5
26
25 DB11
DB4
4
DGND
DB3
5
6
25 DB11
V
V
24
23
22
5
DGND
DB3
SS
24
SS
AGND
6
DB2
DB1
DB0
23 AGND
7
8
9
AD7886
AD7886
TOP VIEW
V
DB2
7
REF
V
TOP VIEW
(Not to Scale)
22
21 SUM
REF
(Not to Scale)
DB1
8
21 SUM
+5REF
DB0
9
20
19
18
17
16
15
V
+5REF
20
19
10
11
DD
V
V
DD
10
11
12
13
14
DD
V
BUSY
DD
VIN2
VIN1
BUSY
CS
12
13 14 15 16 17 18
AGND
RD
V
CONVST
SS
TERMINOLOGY
Unipolar Offset Error
result. The 12 bits of data are then stored internally in a three-
state output latch.
The ideal first code transition should occur when the analog
input is 1 LSB above AGND. The deviation of the actual transi-
tion from that point is termed the offset error.
REFERENCE INPUT
Bipolar Zero Error
The AD7886 operates from a 3.5 V reference, which must be
provided at the VREF input. Two on-chip resistors for use with
an external amplifier can be used for deriving 3.5 V from stan-
dard 5 V references. Figure 2 shows an example with the AD586
which a is a high performance voltage reference exhibiting
excellent stability performance, 5 ppm/°C max. The external
amplifier serves a second function of force/sensing the VREF
input. Force/sensing minimizes error contributions from
The ideal midscale transition (i.e., 0111 1111 1111 to 1000
0000 0000) for the +5 V range should occur when the analog
input is at zero volts. Bipolar zero error is the deviation of the
actual transition from that point.
Gain Error
In the unipolar mode, gain error is measured with respect to the
first and last code transition points. The ideal difference be-
tween these points is FS–2 LSBs. For bipolar applications, the
gain error is measured from the midscale transition to both the
first and last code transitions. The ideal difference in this case is
FS/2–1 LSB. The gain error is defined as the deviation between
the ideal difference, given above, and the measured difference.
For the bipolar case, there are two gain errors; the figure in the
specification page represents the worst case. Ideal FS depends
on the +5REF input; for the 0 V to 5 V input, ideal FS = +5REF
and for the 0 V to 10 V and +5 V ranges, ideal FS = 2 × + 5REF.
+V
+V
IN
+5REF
SUM
+5V
V
OUT
AD586
GND
R1
9k
AD7886*
R2
6.3k
CONVERTER DETAILS
AD707
The AD7886 is a triple-pass flash ADC that uses 15 compara-
tors in a 4-bit flash technique to perform the 12-bit conversion
procedure. Each of the 4096 quantization levels is realized inter-
nally with a precision resistor DAC.
V
–
+
–3.5V
REF
TO DAC
AGND
The fifteen comparators first compare the analog input voltage
to the VREF/16 voltages of the resistor array. This determines the
four most significant bits and selects 1 out of 16 voltage seg-
ments. The comparators are then switched to 15 subvoltages on
that segment to determine the next four bits and select 1 out of
256 voltage segments. A further switching of the comparators to
another 15 subvoltages produces the complete 12-bit conversion
C1
10µF
C2
0.1µF
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Typical Reference Circuitry
REV. B
–5–
ADI [ ADI ]
