AD9059
N
N+3
N+5
PIN DESCRIPTIONS
AIN
N+1
N+2
N+4
Pin No.
1, 28
2
Name
Function
AINA, AINB Analog Inputs for ADC A and B.
VREF
Internal Voltage Reference (+2.5 V
Typical); Bypass with 0.1
µF
to
Ground or Overdrive with External
Voltage Reference.
Power-Down Function Select;
Logic HIGH for Power-Down
Mode (Digital Outputs Go to High-
Impedance State).
Analog +5 V Power Supply.
Ground.
Digital Output Power Supply.
Nominally +3 V to +5 V.
Digital Outputs of ADCA.
Digital Outputs of ADCB.
Encode Clock for ADCs A and B
(ADCs Sample Simultaneously On
the Rising Edge of ENCODE).
t
A
ENCODE
t
EH
t
EL
t
V
DIGITAL
OUTPUTS
N–3
N–2
N–1
N
N+1
N+2
3
PWRDN
t
PD
MIN
t
A
t
EH
t
EL
t
V
t
PD
APERTURE DELAY
PULSE WIDTH HIGH
PULSE WIDTH LOW
OUTPUT VALID TIME
OUTPUT PROP DELAY
6.7ns
6.7ns
4.0ns
6.6ns
9.5ns
14.2ns
TYP
2.7ns
MAX
166ns
166ns
4, 25
5, 24, 27
6, 23
7–14
22–15
26
V
D
GND
V
DD
D7A–D0A
D7B–D0B
ENCODE
Figure 1. Timing Diagram
PIN CONFIGURATION
AINA 1
VREF 2
PWRDN 3
V
D
4
GND 5
V
DD
6
28 AINB
27 GND
26 ENCODE
25 V
D
Table I. Digital Coding (VREF = +2.5 V)
Analog Input
3.0 V
2.502 V
2.498 V
2.0 V
Voltage Level
Positive Full Scale
Midscale + 1/2 LSB
Midscale – 1/2 LSB
Negative Full Scale
Digital Output
1111 1111
1000 0000
0111 1111
0000 0000
AD9059
24 GND
23 V
DD
TOP VIEW
D7A (MSB) 7 (Not to Scale) 22 D7B (MSB)
D6A 8
D5A 9
D4A 10
D3A 11
D2A 12
D1A 13
D0A (LSB) 14
21 D6B
20 D5B
19 D4B
18 D3B
17 D2B
16 D1B
15 D0B (LSB)
–4–
REV. 0
AD [ ANALOG DEVICES ]
