AD9059
THEORY OF OPERATION
The AD9059 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology
to provide dual high performance 8-bit ADCs in a single low
cost monolithic device. The design architecture ensures low
power, high speed, and 8-bit accuracy.
The AD9059 provides two linked ADC channels that are
clocked from a single ENCODE input (refer to block diagram).
The two ADC channels simultaneously sample the analog in-
puts (AINA and AINB) and provide non-interleaved parallel
digital outputs (D0A–D7A and D0B–D7B). The voltage refer-
ence (VREF) is internally connected to both ADCs so channel
gains and offsets will track if external reference control is
desired.
The analog input signal is buffered at the input of each ADC
channel and applied to a high speed track-and-hold. The T/H
circuit holds the analog input value during the conversion pro-
cess (beginning with the rising edge of the ENCODE com-
mand). The T/H’s output signal passes through the gray code
and flash conversion stages to generate coarse and fine digital
representations of the held analog input level. Decode logic
combines the multistage data and aligns the 8-bit word for
strobed outputs on the rising edge of the ENCODE command.
The MagAmp/Flash architecture of the AD9059 results in three
pipeline delays for the output data.
USING THE AD9059
Analog Inputs
applied to the VREF pin to overdrive the internal voltage refer-
ence for gain adjustment of up to
±
10% (the VREF pin is inter-
nally tied directly to the ADC circuitry). ADC gain and offset
will vary simultaneously with external reference adjustment with
a 1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC offset by 50 mV).
Theoretical input voltage range versus reference input voltage
may be calculated from the following equations:
V
RANGE
(p-p) = VREF/2.5
V
MIDSCALE
= VREF
V
TOP-OF-RANGE
= VREF + V
RANGE
/2
V
BOTTOM-OF-RANGE
= VREF – V
RANGE
/2
The external reference should have a 1 mA minimum sink/
source current capability to ensure complete overdrive of the
internal voltage reference.
Digital Logic (+5 V/+3 V Systems)
The digital inputs and outputs of the AD9059 can easily be
configured to interface directly with +3 V or +5 V logic systems.
The encode and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat-
ible with TTL, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.
The AD9059’s digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. The voltage supply pins
(V
DD
) for these CMOS stages are isolated from the analog V
D
voltage supply. By varying the voltage on these supply pins the
digital output HIGH levels will change for +5 V or +3 V sys-
tems. The V
DD
pins are internally connected on the AD9059
die. Care should be taken to isolate the V
DD
supply voltages
from the +5 V analog supply to minimize noise coupling into
the ADCs.
The AD9059 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should
be provided before a high impedance characteristic is required.
A 200 ns power-up period should be provided to ensure accu-
rate ADC output data after reactivation (valid output data is
available three clock cycles after the 200 ns delay).
Timing
The AD9059 provides independent single-ended high imped-
ance (150 kΩ) analog inputs for the dual ADCs. Each input
requires a dc bias current of 6
µA
(typical) centered near +2.5 V
(± 10%). The dc bias may be provided by the user or may be
derived from the ADC’s internal voltage reference. Figure 14
shows a low cost dc bias implementation allowing the user to
capacitively couple ac signals directly into the ADC without ad-
ditional active circuitry. For best dynamic performance the
VREF pin should be decoupled to ground with a 0.1
µF
capaci-
tor (to minimize modulation of the reference voltage), and the
bias resistor should approximately 1 kΩ.
Figure 15 shows typical connections for high performance dc bi-
asing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single +5 V supply (example
analog input signals are referenced to ground).
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9059 (VREF). The reference output is used to set the ADC
gain/offset and can provide dc bias for the analog input signals.
The internal reference is tied to the ADC circuitry through a
800
Ω
internal impedance and is capable of providing 300
µA
external drive current (for dc biasing the analog input or other
user circuitry).
Some applications may require greater accuracy, improved tem-
perature performance, or gain adjustments which cannot be ob-
tained using the internal reference. An external voltage may be
The AD9059 is guaranteed to operate with conversion rates
from 5 MSPS to 60 MSPS. At 60 MSPS the ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulse width variations of
up to
±
10% (allowing the encode signal to meet the minimum/
maximum HIGH/LOW specifications) will cause no degrada-
tion in ADC performance (refer to Figure 1 Timing Diagram).
Due to the linked ENCODE architecture of the ADCs, the
AD9059 cannot be operated in a two-channel ping-pong mode.
REV. 0
–7–
AD [ ANALOG DEVICES ]
