ADSP-2181
P aram eter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
50
20
20
150
ns
ns
ns
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 7
0.5tCK – 7
0
ns
ns
ns
20
Contr ol Signals
Timing Requirement:
1
tRSP
RESET Width Low
5tCK
ns
NOT E
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(2:0)*
tMH
tMS
RESET
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 8. Clock Signals
REV. D
–14–
ADI [ ADI ]
