OP177
@ V
S
= ±15 V, −40°C ≤ T
A
≤ +85°C, unless otherwise noted.
Table 2.
Parameter
INPUT
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Current
Average Input Offset Current Drift
Input Bias Current
Average Input Bias Current Drift
2
Input Voltage Range
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
4
OUTPUT VOLTAGE SWING
POWER CONSUMPTION
SUPPLY CURRENT
1
2
Symbol
V
OS
TCV
OS
I
OS
TCI
OS
I
B
TCI
B
IVR
CMRR
PSRR
A
VO
V
O
P
D
I
SY
Conditions
Min
OP177F
Typ
15
0.1
0.5
1.5
+2.4
8
±13.5
140
120
6000
±13
60
20
Max
40
0.3
2.2
40
+4
40
Min
OP177G
Typ
20
0.7
0.5
1.5
+2.4
15
±13.5
140
115
4000
±13
60
2
Max
100
1.2
4.5
85
±6
60
Unit
μV
μV/°C
nA
pA/°C
nA
pA/°C
V
dB
dB
V/mV
V
mW
mA
−0.2
±13
120
110
2000
±12
V
CM
= ±13 V
V
S
= ±3 V to ±18 V
R
L
≥ 2 kΩ, V
O
= ±10 V
R
L
≥ 2 kΩ
V
S
= ±15 V, no load
V
S
= ±15 V, no load
±13
110
106
1000
±12
75
2.5
75
2.5
TCV
OS
is sample tested.
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ±10 V output range, A
VO
is tested at −10 V ≤ V
O
≤ 0 V, 0 V ≤ V
O
≤ +10 V, and −10 V ≤ V
O
≤ +10 V.
TEST CIRCUITS
200kΩ
50Ω
–
OP177
+
V
OS
=
V
O
4000
V
O
00289-003
Figure 3. Typical Offset Voltage Test Circuit
20kΩ
V+
–
INPUT
+
–
OP177
+
OUTPUT
V–
Figure 4. Optional Offset Nulling Circuit
20kΩ
+20V
–
OP177
+
PINOUTS SHOWN FOR
P AND Z PACKAGES
–20V
00289-005
Figure 5. Burn-In Circuit
Rev. E | Page 4 of 16
00289-004
V
OS
TRIM RANGE IS
TYPICALLY ±3.0mV
AD [ ANALOG DEVICES ]
