USS-820FD
USB Device Controller
Data Sheet, Rev. 1
August 2004
Firmware Responsibilities for USB
SETUP Commands
(continued)
Firmware must keep track of the direction of data flow
during a control transfer, and detect the start of the
status stage by a change in that direction. For control
OUT transfers, the status stage will be an IN, and the
firmware should write a zero-byte data packet to the
transmit FIFO, assuming the command completed
successfully. For control IN transfers, the status stage
will be an OUT, and the firmware should read the data
packet and set the RXFFRC register bit (like any other
OUT transfer), again assuming the command
completed successfully. This will cause an ACK to be
sent to the host, indicating a successful completion.
Firmware should stall endpoint 0 if it receives a stan-
dard command that does not match any of the defined
commands or a valid command that contains a param-
eter with a bad value (e.g., GET_STATUS[Endpoint x]
when endpoint x is not enabled). Firmware should also
stall if the data stage of a control transaction attempts
to transfer more bytes than were indicated by the
SETUP stage.
Firmware must interpret any vendor or class
commands as defined by the application.
Frame Timer Behavior
The USS-820FD contains an internal frame timer that
allows the device to lock to the USB host frame timer,
and to synthesize lost SOF packets, as required by the
USB specification. The frame timer requires three valid
SOF packets from the host in order to lock to the host
frame timer. This locked status is indicated by the
FTLOCK status bit in SOFH. In order to achieve this
lock, the interval between each SOF must be within
45 clocks of the nominal 12,000 clocks, and the
successive intervals must be within two clocks of each
other. Both of these conditions will be true in a correctly
functioning system with no bus errors. While the frame
timer is locked, it will synthesize SOFs by setting
ASOF, generating an SOF interrupt (if SOFIE = 1), and
asserting the SOFN pin (if SOFODIS = 0) for up to
three consecutive frames if SOF packets are no longer
received from the host. The frame timer will become
unlocked under any of the following conditions:
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Hard or soft reset.
USB reset.
The device goes suspended.
No SOF packets are received from the host for three
frames.
An SOF is received that violates the USB specifica-
tion for frame interval or previous frame length com-
parison.
Other Firmware Responsibilities
Table 41. Other Firmware Responsibilities
USB Event
Firmware Responsibility
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USB Reset USB reset can be detected by reading a
1 from the RESET bit of the SSR
register. If the USB interrupt is enabled
(IE_RESET), this will be indicated by the
IRQN output. At that time, firmware
must reset any information it maintains
regarding endpoints, interfaces, alter-
nate settings, and configurations. All
RXEPEN and TXEPEN endpoints
should be set to 0, except for endpoint
0, which should be set to 1. The function
address register FADDR should be set
to 0. The data toggle bits for all
endpoints should be set to 0 as well. If
MCSR.FEAT = 1, FADDR is automati-
cally cleared to 0 when USB reset is
detected.
Firmware must manage the SUSPEND
USB
Suspend and RESUME register bits, as docu-
mented in the following section, in order
and
to meet the USB specifications for bus-
Resume
powered devices.
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Suspend and Resume Behavior
Note:
In the following sections describing suspend and
resume behavior, the following terminology is
used:
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Device—The entire product that contains the USS-
820FD, such as a modem or printer.
Application—All electronic components of the device
other than the USS-820FD, such as a microcontrol-
ler, RAM, power control logic, reset logic, or crystal.
Firmware—Code running on the microcontroller
which is part of the application.
Controller—That intelligent part of the application
which uses the USS-820FD address, data and read/
write pins to access its internal registers.
Powered-off components—Those parts of the appli-
cation which are connected to the USS-820FD and
powered off during suspend, for example, a micro-
controller or RAM.
Hardware—Logic inside the USS-820FD.
Agere Systems Inc.
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AGERE [ AGERE SYSTEMS ]
