USS-820FD
USB Device Controller
Data Sheet, Rev. 1
August 2004
Interrupts
Each status bit has a corresponding enable bit that allows the event to cause an interrupt. Interrupts can be
masked globally by the T_IRQ bit of the SCR register. The active level and signaling mode (level vs. pulse) of the
IRQN output pin can be controlled by the IRQPOL and IRQLVL bits of the SCR register. All interrupts have equal
priority—firmware establishes its own priority by the order in which it checks these status bits during interrupt
processing.
USB RESET
RESET
IE_RESET
USB SUSPEND
SUSPEND
IE_SUSP
T_IRQ
RISING EDGE
DETECT
&
PULSE
GENERATE
IRQPOL
USB RESUME
RESUME
IE_RESUME
INTERRUPT
PRESENT
I
O
IRQN PIN
USB START OF FRAME
PSEUDO START OF FRAME
ASOF
SOFIE
IRQLVL
ENDPOINT 7 RECEIVE COMPLETE
SBI1[7]
SBIE1[7]
ENDPOINT 0 RECEIVE COMPLETE
SBI[1]
SBIE[1]
ENDPOINT 7 TRANSMIT COMPLETE
SBI1[6]
SBIE1[6]
ENDPOINT 0 TRANSMIT COMPLETE
SBI[0]
SBIE[0]
5-6402
Figure 7. USS-820FD Interrupts
40
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
