Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
BRI9
I9
BL09
BR09
BRI9
BL09
BR09
BLI9
I9
BLI9
BRI8
I8
BL08
BR08
BRI8
BL08
BR08
I8
BLI8
BLI8
BRI7
I7
BRI7
BL07
BR07
BL07
BR07
I7
BLI7
BRI6
BLI7
BL06
BR06
BRI6
I6
BL06
BR06
I6
BLI6
BLI6
BRI5
BL05
BR05
I5
BRI5
I5
BL05
BR05
BLI5
DEC
BLI5
BRI4
BL04
BR04
I4
BLI4
BRI4
I4
BL04
BR04
TRI
BLI4
0/1
0/1
0/1
TRI
DEC
HIGH Z WHEN LOW
0/1
0/1
1
0
DEC
0/1
HIGH Z WHEN LOW
THIS CAN BE USED
TO GENERATE
A VHI OR VLO
BRI3
I3
BL03
BR03
BLI3
BRI2
I2
BL02
BR02
BRI3
I3
BL03
BLI2
BR03
BLI3
BRI1
I1
BL01
BR01
BRI2
I2
BL02
BR02
BLI1
BLI2
BRI0
I0
BL00
BR00
BRI1
I1
BLI0
BL01
BR01
5-5744(F)
BLI1
Figure 11. SLIC All Modes Diagram
BRI0
I0
BL00
BR00
BLI0
5-5745(F)
Figure 12. Buffer Mode
22
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
