Data Sheet
June 1999
ORCA
Series 3C and 3T FPGAs
of up to 10 bits. Each group of buffers can feed into an
AND gate (4-input AND for the nibble groups and 2-
input AND for the other two buffers). These AND gates
then feed into a 3-input gate that can be configured as
either an AND gate or an OR gate. The output of the 3-
input gate is invertible and is output at the DEC output
of the SLIC. Figure 16 shows the SLIC in full decoder
mode.
The functionality of the SLIC is parsed by the two
nibble-wide groups and the 2-bit buffer group. Each of
these groups may operate independently as BIDI buff-
ers (with or without 3-state capability for the nibble-
wide groups) or as a
PAL/decoder.
As discussed in the memory mode section, if the SLIC
is placed into one of the modes where it contains both
buffers and a decode or AOI function (e.g.,
BUF_BUF_DEC mode), the DEC output can be gated
with the 3-state input signal. This allows up to a 6-input
decode (e.g., BUF_DEC_DEC mode) plus the 3-state
input to control the enable/disable of up to four buffers
per SLIC. Figure 12—Figure 16 show several configu-
rations of the SLIC, while Table 6 shows all of the possi-
ble modes.
Table 6. SLIC Modes
Mode
#
1
2
3
4
5
6
7
8
Programmable Logic Cells
(continued)
Supplemental Logic and Interconnect Cell
(SLIC)
Each PLC contains a supplemental logic and intercon-
nect cell (SLIC) embedded within the PLC routing, out-
side of the PFU. As its name indicates, the SLIC
performs both logic and interconnect (routing) func-
tions. Its main features are 3-statable, bidirectional buff-
ers, and a
PAL-like
decoder capability. Figure 11 shows
a diagram of a SLIC with all of its features shown. All
modes of the SLIC are not available at one time.
Each SLIC contains ten bidirectional (BIDI) buffers,
each buffer capable of driving left and/or right out of the
SLIC. These BIDI buffers are twin-quad in nature and
are segregated into two groups of four (nibbles) and a
third group of two for control. Each of these groups of
BIDIs can drive from the left (BLI[9:0]) to the right
(BRO[9:0]), the right (BRI[9:0]) to the left (BLO[9:0]), or
from the central input (I[9:0]) to the left and/or right.
This central input comes directly from the PFU outputs
(O[9:0]). Each of the BIDIs in the nibble-wide groups
also has a 3-state buffer capability, but not the third
group.
There is one 3-state control (TRI) for each SLIC, with
the capability to invert or disable the 3-state control for
each group of four BIDIs. Separate 3-state control for
each nibble-wide group is achievable by using the
SLIC’s decoder (DEC) output, driven by the group of
two BIDIs, to control the 3-state of one BIDI nibble
while using the TRI signal to control the 3-state of the
other BIDI nibble. Figure 12 and Figure 13 show the
SLIC in buffer mode with available 3-state control from
the TRI and DEC signals. If the entire SLIC is acting in
a buffer capacity, the DEC output may be used to gen-
erate a constant logic 1 (VHI) or logic 0 (VLO) signal for
general use.
The SLIC may also be used to generate
PAL-like
AND-
OR with optional INVERT (AOI) functions or a decoder
Mode
BUFFER
BUF_BUF_DEC
BUF_DEC_BUF
BUF_DEC_DEC
BUF
[3:0]
Buffer
Buffer
Buffer
Buffer
BUF
[7:4]
Buffer
Buffer
Decoder
Buffer
Buffer
BUF
[9:8]
Buffer
Decoder
Buffer
Buffer
Decoder
Buffer
Decoder Decoder
DEC_BUF_BUF Decoder
DEC_BUF_DEC Decoder
DECODER
DEC_DEC_BUF Decoder Decoder
Decoder Decoder Decoder
Lucent Technologies Inc.
21
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