Data Sheet
February 1998
T7502 Dual PCM Codec with Filters
Features
s
s
s
s
Applications
s
s
s
+5 V only
Automatic powerdown mode
Low-power, latch-up-free CMOS technology
On-chip sample and hold, autozero, and precision
voltage reference
Differential architecture for high noise immunity
and power supply rejection
Automatic master clock frequency selection
2.048 MHz or 4.096 MHz fixed data rate
Frame sync controlled channel swapping
Differential analog I/O
300
Ω
output drivers
Operating temperature range: –40
°
C to +85
°
C
A-law companding
Speakerphone
Telephone answering device (TAD)
POTS for ISDN
Description
The T7502 device is a single-chip, two-channel
A-law PCM codec with filters. This integrated circuit
provides analog-to-digital and digital-to-analog
conversion. It provides the transmit and receive
filtering necessary to interface a voice telephone
circuit to a time-division multiplexed (TDM) system.
The device features a differential transmit amplifier,
and the power receive amplifier is capable of driving
600
Ω
differentially. PCM timing is defined by a single
frame sync pulse. This device operates in a delayed
timing mode (digital data is valid one clock cycle after
frame sync goes high). The T7502 is packaged in a
20-pin SOJ.
s
s
s
s
s
s
s
s
GS
X
0
D
X
VF
X
IN0
VF
X
IP0
VCM0
–
+
+2.4 V
FILTER
NETWORK
ENCODER
PCM
INTERFACE
D
R
GNDD
CHANNEL 0
FS
VF
R
OP0
VF
R
ON0
FILTER
NETWORK
DECODER
POWERDOWN
CONTROL
INTERNAL TIMING
& CONTROL
GS
X
1
VF
X
IN1
VF
X
IP1
VCM1
VF
R
OP1
VF
R
ON1
CHANNEL 1
BIAS
CIRCUITRY
&
REFERENCE
V
DD
(1)
GNDA (2)
MCLK
5-3609.b
Figure 1. Block Diagram
AGERE [ AGERE SYSTEMS ]
