Data Sheet
February 1998
T7502 Dual PCM Codec with Filters
Pin Information (continued)
Table 1. Pin Descriptions
Symbol
Pin
Type
Name/Function
VFXIN1
VFXIN0
17
4
I
Voice Frequency Transmitter Negative Input. Analog inverting input to the
uncommitted operational amplifier at the transmit filter input.
VFXIP1
VFXIP0
16
5
I
Voice Frequency Transmitter Positive Input. Analog noninverting input to the
uncommitted operational amplifier at the transmit filter input.
GSX1
GSX0
15
6
O
O
O
—
Gain Set for Transmitter. Output of the transmit uncommitted operational amplifi-
er. The pin is the input to the transmit differential filters.
VFROP1
VFROP0
20
1
Voice Frequency Receiver Positive Output. This pin can drive ≥300 Ω loads.
VFRON1
VFRON0
19
2
Voice Frequency Receiver Negative Output. This pin can drive ≥300 Ω loads.
VDD
8
+5 V Power Supply. This pin should be bypassed to analog ground with at least
0.1 µF of capacitance as close to the device as possible. VDD serves both analog
and digital internal circuits.
GNDA1
GNDA0
18
3
—
I
Analog Grounds. Both ground pins must be connected on the circuit board. AGND
serves both analog and digital internal circuits.
DR
12
Receive PCM Data Input. The data on this pin is shifted into the device on the fall-
ing edges of MCLK. Sixteen consecutive bits of data (8 bits for channel 0, and
8 bits for channel 1) are entered after the FS pulse has been detected.
DX
11
O
I
Transmit PCM Data Output. This pin remains in the high-impedance state except
during active transmit time slots. Sixteen consecutive bits of data (8 bits for
channel 0 and 8 bits for channel 1) are shifted out on the rising edge of MCLK. Data
is shifted out on the rising edge of MCLK.
MCLK
9
Master Clock Input. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is re-
quired.
GNDD
FS
10
13
—
Id*
Digital Ground. Ground connection for the digital circuitry.
Frame Sync. This signal is an edge trigger and must be high for a minimum of one
MCLK cycle. This signal must be derived from MCLK. If FS is low for 500 µs while
MCLK remains active, then the device fully powers down. An internal pull-down de-
vice is included on FS.
VCM0
VCM1
7
14
O
Voltage Common Mode. 2.4 Vdc.
d
* I indicates a pull-down device is included on this lead.
Lucent Technologies Inc.
3
AGERE [ AGERE SYSTEMS ]
