Data Sheet
February 1998
T7502 Dual PCM Codec with Filters
Functional Description
The T7502 has one frame sync (FS) input that determines transmit and receive data timing for both channels. The
width of the FS pulse determines the order of the two channels on the PCM buses. If FS is nominally one MCLK
period wide (see Figure 5), the data for channel 0 is first. If FS is nominally two or more MCLK periods wide (Figure
6), the data for channel 1 is first. During a single 125 µs frame, the frame sync input is supplied a single pulse.
The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the
master clock frequency during the powerup reset interval.
Powerdown is achieved by removing the FS pulse for at least 500 µs with MCLK active, after which MCLK may be
removed. Both channels are powered down together. Powerdown is not guaranteed if MCLK is lost, unless the
device is already in the powerdown mode.
GSXn
VFXINn
VFXIPn
RFN
RIN
RIP
TO
CODEC
FILTERS
–
+
VCM0
2.4 V
RFN
RIN
RFP
GAIN =
5-3787
Figure 2.Typical Analog Input Section
Pin Information
VFROP0
VFRON0
GNDA0
VFXIN0
VFXIP0
GSX0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VFROP1
VFRON1
GNDA1
VFXIN1
VFXIP1
GSX1
VCM1
FS
T - 7502 - - - EL
VCM0
VDD
MCLK
DR
GNDD
DX
5-3788.a
Figure 3. Pin Diagram
2
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
