Data Sheet
August 1999
T7507 Quad PCM Codec with Filters,
Termination Impedance, and Hybrid Balance
Microprocessor Interface
Table 24. T7507 Microprocessor Interface Timing
Frequency of CCLK = 2.048 MHz.
Symbol
tCCLCCH
tCCHCCL
tCCHCCH
tCCH1CCH2
tCCL1CCL2
tCSLCCL
tCCLCSH
tCIVCCL
tCCLCIX
tCSHCSL
tSU1BO2
tSU2BO1
tSU1RD
tSU2RD
tENL
Parameter
Time of CCLK Low
Time of CCLK High
Period of CCLK
Rise Time of CCLK
Fall Time of CCLK
CSEL
Low to CCLK Transition
Test Conditions
Min
160
160
488
—
—
50
30
50
50
50
488
488
488
488
977
Max
—
—
—
50
50
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
Measured from first
CCLK low transition
Measured from eighth
CCLK Low to
CSEL
High
CCLK low transition
Setup Time, Data Input/Output Valid to CCLK Low
—
Hold Time, CCLK Low to Data Input/Output Invalid
—
Minimum Time Between Writes
—
Setup Time for B0—B1 Data
—
Setup Time for B0—B1 Data
—
Setup Time for RD1, RD2, RD3 Data
—
Setup Time for RD1, RD2, RD3 Data
—
Enable Pulse Width
—
Lucent Technologies Inc.
23
AGERE [ AGERE SYSTEMS ]
