Data Sheet
August 1999
T7507 Quad PCM Codec with Filters,
Termination Impedance, and Hybrid Balance
Timing Characteristics
Table 25. Clock Section
See Figures 12—14.
Symbol
tMCHMCL1
tCDC
tMCH1MCH2
tMCL2MCL1
Parameter
Clock Pulse Width
Duty Cycle, MC
Clock Rise and
Fall Time
Test Conditions
—
—
—
Min
97
40
0
Typ
—
—
—
Max
—
60
15
Unit
ns
%
ns
Table 26. T7507 Transmit Section (Delayed Timing)
See Figure 12.
Symbol
tMCHDV
tMCHDV1
tMCLDZ*
tSPHMCL
tMCLSPH
tSPLMCL
tSPHSPL
Parameter
Data Enabled on TS Entry
Data Delay from MC
Data Float on TS Exit
Frame-sync Hold Time
Frame-sync High Setup
Frame-sync Low Setup
Frame-sync Pulse Width
Test Conditions
0 < C
LOAD
< 100 pF
0 < C
LOAD
< 100 pF
C
LOAD
= 0
—
—
—
—
Min
0
0
15
50
50
50
0.1
Typ
—
—
—
—
—
—
—
Max
60
60
100
—
—
—
125 – tMCHMCH
Unit
ns
ns
ns
ns
ns
ns
µs
* Timing parameter tMCLDZ is referenced to a high-impedance state.
Table 27. T7507 Transmit Section (Nondelayed Timing)
See Figure 13.
Symbol
tSPHDV
tMCHDV1
tMCHDZ*
tSPHMCL
tMCLSPH
tSPLMCL
tSPHSPL
Parameter
Data Enabled on TS Entry
Data Delay from FS
X
Data Float on TS Exit
Frame-sync Hold Time
Frame-sync High Setup
Frame-sync Low Setup
Frame-sync Pulse Width
Test Conditions
0 < C
LOAD
< 100 pF
0 < C
LOAD
< 100 pF
C
LOAD
= 0
—
—
—
—
Min
0
0
0
50
50
50
0.1
Typ
—
—
—
—
—
—
—
Max
80
60
30
—
—
—
125 – tMCHMCH
Unit
ns
ns
ns
ns
ns
ns
µs
* Timing parameter tMCHDZ is referenced to a high-impedance state.
Table 28. T7507 Receive Section
See Figures 12—14.
Symbol
tDVMCL
tMCLDV
tSPHMCL
tSPLMCL
Parameter
Receive Data Setup
Receive Data Hold
Frame Separation Hold Time
Frame Separation Low Setup
Test Conditions
—
—
—
—
Min
30
15
50
50
Typ
—
—
—
—
Max
—
—
—
—
Unit
ns
ns
ns
ns
Lucent Technologies Inc.
25
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