T8301 Internet Protocol Telephone
Phone-On-A-Chip
IP Solution DSP
Advance Data Sheet
December 2000
4 DSP1600 Core
(continued)
4.4 Bit Input/Output (BIO)
The BIO provides convenient and efficient monitoring and control of four individually configurable pins. When con-
figured as outputs, the pins can be individually set, cleared, or toggled. When configured as inputs, individual pins
or combinations of pins can be tested for patterns. Flags returned by the BIO mesh seamlessly with conditional
instructions. Although the DSP1627 has eight BIOs available, the T8301 makes the four low-order BIOs available
on pins.
4.5 Serial Input/Output (SIO)
The serial I/O interface (SIO) of the T8301 closely follows the serial interface of the DSP1627. The T8301 multi-
plexes certain DSP1627 SIO pins and eliminates some others to reduce the total pin count. Hysteresis input buffers
are used for the SIO clocks on this device (IOLD,
IOCK,
and
SYNC).
The table below shows the signals that com-
prise the T8301 SIO interface.
Table 2. SIO Interface Signals
Symbol
DI1
DO1
IOLD*
IOCK
SYNC
Type
I
Serial data in 1.
O
I/O
I/O
I/O
Serial data out 1.
Input/output load for SIO 1.
Input/output clock for SIO 1.
Sync for SIO 1 and 2.
Function
* IOLD
is comprised of the
ILD1
and the
OLD1
signals from the DSP1627 core tied together. By default, the
IOLD
signal is an input, which cor-
responds to the two DSP1627 load signals configured as passive. However, input load 1 (ILD1) may be configured as active, which then con-
figures the
IOLD
signal as an output. In this case, the internal input load 1 (ILD1) drives the output load signal (OLD1.)
IOCK
is analogous to
IOLD.
Input clock 1 can be configured as an output, which would then drive
IOCK
and
OCK1.
If the PLL is enabled, care should be taken if using
IOCK
as an output since there may be an unacceptable amount
of jitter on the clock.
The
SYNC
signal is intended to provide synchronization of the serial bus with an external 8 kHz frame clock. When
SYNC
is configured as an input and asserted, the SIO load counter is reset and
IOLD
is asserted (if configured as
an output).
For typical applications, the SIO will be configured to have
SYNC
and
IOCK
as inputs and
IOLD
as an output (from
the DSP1627 core). In this configuration, there are thirty-two 8-bit (sixteen 16-bit) time slots for each SIO channel
and
SYNC
provides the 8 kHz SIO frame timing. The timing relationship for this configuration can be found in the
DSP1627 data sheet.
4.6 Interrupts and Traps
The DSP1627 supports prioritized, vectored interrupts, and a trap. There are eight internal hardware sources for
program interrupt and two external interrupt pins. Additionally, there is a trap signal from the hardware development
system (HDS). Each of the sources has a unique vector address and priority assigned to it. Refer to the DSP1627
data sheet for more information.
The use of the two external DSP1627 core interrupts is shown in Table 3 and in Figure 2.
10
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
