Data Sheet, Revision 3
September 21, 2005
TSI-2
2k x 2k Time-Slot Interchanger
5 Timing Diagrams and ac Characteristics
Figure 5-1 and Figure 5-2 describe the timing specifications for the input clocks
t2
t1
t3
VDD33
VIH
VIH
t4
50%
VIL
VIL
Figure 5-1. CHICLK Timing Specifications
Table 5-1. CHICLK Timing Specifications
Parameter
Description
CHICLK Rise Time
Min
Typ
Max
Unit
t1
t2
t2
t3
t4
t4
—
48.84
24.42
—
2
—
7
73.24
36.62
7
ns
ns
ns
ns
ns
ns
CHICLK Width (8.192 MHz)*
CHICLK Width (16.384 MHz)*
CHICLK Fall Time
—
2
CHICLK Period (8.192 MHz)
CHICLK Period (16.384 MHz)
—
122.07
61.03
—
—
—
* VIH to VIH or VIL to VIL.
t6
t5
t7
VDD33
VIH
VIH
t8
50%
VIL
VIL
Figure 5-2. MPUCLK Timing Specifications
Table 5-2. MPUCLK Timing Specifications
Parameter
Description
MPUCLK Rise Time
Min
Typ
Max
Unit
t5
t6
t7
t8
—
6.06
—
2
—
2
7
—
7
ns
ns
ns
ns
MPUCLK Width*
MPUCLK Fall Time
MPUCLK Period
15.2
—
—
* VIH to VIH or VIL to VIL.
Agere Systems Inc.
19
AGERE [ AGERE SYSTEMS ]
