Data Sheet, Revision 3
September 21, 2005
TSI-2
2k x 2k Time-Slot Interchanger
FSYNC
t13
t
14
CHICLK
t
15
t16
RXD
TXD
t19
t
18
t17
Note: This figure assumes the device is programmed to sample FSYNC on the rising edge of CHICLK.
Figure 5-4. CHI Interface Timing
Table 5-4. CHI Interface Timing
Parameter
Description
Min
Max
Unit
t13
t14
t15
t16
t17
t18
t19
FSYNC Setup Time to Active CHICLK Edge
FSYNC Hold Time from Active CHICLK Edge
RXD Setup to Active CHICLK Edge
10
5
—
—
—
—
15
12
15
ns
ns
ns
ns
ns
ns
ns
10
5
RXD Hold Time from Active CHICLK Edge
TXD High Z to Data Valid
—
2
TXD Propagation Delay from Active CHICLK Edge
Transmit Data High Impedance*
—
* Applies if Driver_Enable_Control = 01. For Driver_Enable_Control = 11 refer to Figure 5-15, CHI 3-State Output Control on page 27.
All timing specifications apply under the following conditions:
If FS is active-low.
If the falling edge of CHICLK is specified as the active edge.
At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of
16.384 MHz or 8.192 MHz.
Agere Systems Inc.
21
AGERE [ AGERE SYSTEMS ]
