TSI-2
Data Sheet, Revision 3
September 21, 2005
2k x 2k Time-Slot Interchanger
FSYNC
CHICLK
w/ 0 offset
w/ ¼ bit offset
w/ ½ bit offset
w/ ¾ bit offset
w/ bit offset = 1
w/ 2¾ bit offset
w/ bit offset = 7
TS255 B6 TS255 B7
TS255 B6 TS255 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS0 B5
data sampled
TS0 B0
TS0 B1
data sampled
TS0 B2
TS0 B3
TS0 B4
TS0 B5
TS255 B6 TS255 B7
TS0 B0
TS0 B1
data sampled
TS0 B2
TS0 B3
TS0 B4
TS0 B5
TS255 B5 TS255 B6 TS255 B7
TS255 B5 TS255 B6 TS255 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS0 B5
data sampled
TS0 B0
data sampled
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7
data sampled
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS254 B7 TS255 B0 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7
data sampled
TS0 B 0
TS0 B1
TS0 B0
w/ TS offset = 1,
bit offset = 0
TS254 B6 TS254 B7 TS255 B0 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS255 B6 TS255 B7
data sampled
w/ TS offset = 13,
bit offset = 3¼
TS242 B3 TS242 B4 TS242 B5 TS242 B6 TS242 B7 TS243 B0 TS243 B1 TS243 B2 TS243 B3 TS243 B4 TS243 B5
data sampled
w/ TS offset = 255,
bit offset = 7¾
TS255 B6 TS255 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS0 B5
TS0 B6
TS0 B7
TS1 B0
data sampled
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Figure 5-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset
w/ ½ bit offset
w/ bit offset = 1
TS255 B5
TS255 B6
TS255 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS0 B5
TS255 B5
TS255 B6
TS255 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS255 B4
TS254 B5
TS255 B5
TS254 B6
TS255 B6
TS254 B7
TS255 B7
TS255 B0
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
w/ TS offset = 1,
bit offset = 0
TS255 B1
TS255 B2
TS255 B3
TS255 B4
TS255 B5
w/ TS offset = 255,
bit offset = 7½
TS255 B6
TS255 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
TS0 B4
TS0 B5
Notes:
1/4 bit offset not valid with 16 Mbits/s data.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
Figure 5-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK
22
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
