Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Pin Information
(continued)
Table 3. Pin Descriptions
(continued)
Pin
B11
Symbol
TOH_OUTB
Type
TTL
I/O
O/
HI-Z/
Pull-up
O/
HI-Z/
Pull-up
O/
HI-Z/
Pull-up
I
I
I
I
O
O
O
O
—
—
I/
O/
Pull-up
I/
Pull-up
I/Pull-Up
I/
Pull-up
SCHMITT
I/
Pull-up
I/
Pull-up
I/
Pull-up
I/
Pull-up
I/
Pull-up
O/
Open
Drain
I/
Pull-down/
SCHMITT
Description
TOH serial link output for receiver #2.
C11
RX_TOH_CKEN
TTL
Rx TOH serial link clock enable.
C12
RX_TOH_FP
TTL
Rx TOH serial link frame pulse.
E1
E2
F1
F2
J1
J2
L1
L2
E3
F3
U11, V11, W11,
Y11, U12, V12,
W12, Y12
U7, V7, W7, Y7,
V8, W8, Y8
V9
U9
STS_INA_P
STS_INA_N
STS_INB_P
STS_INB_N
STS_OUTA_P
STS_OUTA_N
STS_OUTB_P
STS_OUTB_N
CTAP_REFA
CTAP_REFB
CPU_DATA[7:0]
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
—
—
TTL
LVDS input receiver #1.
LVDS input receiver #1.
LVDS input receiver #2.
LVDS input receiver #2.
LVDS output transmitter #1.
LVDS output transmitter #1.
LVDS output transmitter #2.
LVDS output transmitter #2.
LVDS input center tap (Rx #1) (use 0.01 µF to GND).
LVDS input center tap (Rx #2) (use 0.01 µF to GND).
Central processing unit (CPU) interface data bus.
CPU_ADDR[6:0]
RD_WRN
CS_N
TTL
TTL
TTL
CPU interface address bus.
CPU interface read/write.
Chip select.
M18
M19
M17
A7
B7
V10
SYS_FP
LINE_FP
SYS_CLK
PROT_SW_A
PROT_SW_C
INT_N
TTL
TTL
TTL
TTL
TTL
TTL
System frame pulse for transmitter section.
Line frame pulse for receiver section.
System clock (77.76 MHz).
Protection switching control signal.
Protection switching control signal.
Interrupt output.
W9
RST_N
TTL
Global reset.
Agere Systems Inc.
13
AGERE [ AGERE SYSTEMS ]
