Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Pin Information (continued)
Table 3. Pin Descriptions (continued)
Pin
Y9
Symbol
HIZ_N
Type
TTL
I/O
Description
Global 3-state control.
I/
Pull-up/
SCHMITT
K1
M1
PLL_REF
REF10
—
—
—
I
Reference for PLL (10 kΩ to GND).
1.0 V reference for LVDS reference block. See
Figure 3 on page 16.
M2
M3
M4
REF14
—
—
—
I
1.4 V reference for LVDS reference block. See
Figure 3 on page 16.
LVDS_RESH
LVDS_RESL
—
—
Resistance high input (use 100 Ω to LVDS_RESL
input).
Resistance low input (use 100 Ω to LVDS_RESH
input).
A5
B6
K2
K3
A2
DXP
DXN
PLL_VDDA
PLL_VSSA
TCLK
—
—
—
—
—
—
Temperature-sensing diode (anode +).
Temperature-sensing diode (cathode –).
PLL analog VDD (3.3 V).
—
—
TTL
PLL analog VSS (GND).
I/
JTAG clock input.
Pull-up
A3
A4
TDI
TTL
TTL
I/
JTAG data input.
Pull-up
TMS
I/
JTAG mode select input.
Pull-up
B1
B2
TDO
TRSTN
TTL
TTL
O
I/
JTAG data output.
JTAG reset input.
Pull-up
B3
B4
C3
T1
T2
U1
V1
T3
T4
U2
TSTMD
SCANEN
LVDS_EN
TSTMODE
BYPASS
TTL
TTL
—
I/
Scan test mode input.
Pull-up
I/
Scan mode enable input.
Pull-Up
I/
LVDS enable used during boundary scan (B-S).
Enables CDR test mode.
Pull-up
—
I/
Pull-down
—
I/
Enables bypassing of the 622 MHz clock synthesis
Pull-down with TSTCLK.
TSTCLK
—
I/
Test clock for emulation of 622 MHz clock during PLL
Pull-down bypass.
MRESET
RESETRN
RESETTN
TSTSHFTLD
—
I/
Test mode reset.
Pull-down
—
I/
Resets receiver clock division counter.
Pull-up
—
I/
Resets transmitter clock division counter.
Enables the test mode control register for shifting-in
Pull-up
—
I/
Pull-down selected tests by a serial port.
14
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
