Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Synchronization
The incoming data from the high-speed interface (HSI) can be separated into two STS-12 channels per slice (A
and B).
Example of TTSV02622 alignment.
STREAM A
STREAM B
STREAM A
STREAM B
Figure 4. Alignment of Two STS-12 Streams
There is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting synchro-
nization). These streams can be enabled at a later time without disrupting other streams.
HSI Block Interface
The HSI block should provide two independent 77.76 MHz interfaces. Each interface will consist of a byte-wide
data stream and its recovered clock. There is no requirement for bit alignment since SONET type framing will take
place inside the TTSV02622 device.
Line Interface
The line side will receive/transmit frame-aligned streams of STS-12 data. All frames transmitted to the line will be
aligned to the line frame pulse, which will be provided to the TTSV02622. All frames received from the line will be
aligned to the system frame pulse, which will be supplied to the TTSV02622.
Architecture
The TTSV02622 is composed of transmit (Tx) and receive (Rx) sections. The device (see Figure 1 on page 2)
receives two byte-wide data streams at 77.76 MHz (STS-12 rate) and the associated clock. The incoming streams
are framed, and descrambled before they are then written into a FIFO that absorbs phase and delay variations and
allows the shift to system clock. The TOH is then extracted and sent out on the two serial ports. The pointer inter-
preter will then put the synchronous transport signal (STS) synchronous payload envelopes (SPEs) into a small
elastic store from which the pointer generator will produce two byte-wide STS-12 streams of data that are aligned
to the line timing pulse.
Agere Systems Inc.
17
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