TTSV02622 STS-24 Backplane Transceiver
Data Sheet
June 2003
Architecture
(continued)
TOH CLK
TX TOH CLK ENA
TOH INPUT #1
1
1
1
LINE LBPK
(SOFT CTL)
TO RX TOH PROC.
DUAL CHANNEL
TRANSMITTER
TX TOH
PROCESSOR
FRAME
PROC.
TX CH#1
(MACRO)
2
LVDS
OUT #1
INPUT BUS #1
DATA(8)
PARITY(1)
TOH INPUT #2
1
TX TOH
PROCESSOR
INPUT BUS #2
DATA(8)
PARITY(1)
FRAME
PROC.
TX CH#2
(MACRO)
2
LVDS
OUT #2
SYSTEM FRAME
SYSTEM CLOCK
(77.76 MHz)
LINE FRAME
PROT SWITCH A/B
1
1
1
1
CH#1
SOFT CTL
SOFT CTL
FRAME
CLOCK
77.76
MHz
FDBK
REF
77.76
MHz
/8
PLL
622 MHz
622 MHz CLKs
DATA(8)/PARITY(1)
SPE(1) C1J1(1)
OUTPUT BUS #1
RX CH#1
77.76 (MACROCELL)
MHz
CH#2
SOFT CTL
2
LVDS
IN #1
DATA(8)/PARITY(1)
SPE(1) C1J1(1)
OUTPUT BUS #2
POINTER
MOVER
STS-24
FIFO
77.76
MHz
RX CH#2
(MACROCELL)
2
LVDS
IN #2
LVDS LPBK
(SOFT CTL)
SOFT CTL
SOFT CTL
TOH CLK
TOH OUTPUT #1
TOH OUTPUT #2
1
1
SOFT CTL
CH#1
CH#2
RX TOH
PROCESSOR
DUAL CHANNEL
RECEIVER
SOFT CTL
RX TOH CLK ENA
RX TOH FRAME
1
1
CPU INTERFACE (ASYNC)
LINE
SIDE
1
HIZ_N
1
RST_N
(HARD RST)
1
CS_N
1
RD/WR_N
7
ADDR
8
DATA
1
INT_N
LVDS
SIDE
Figure 5. Interior View of TTSV02622
18
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
