TTSV02622 参数 Datasheet PDF下载

Data Sheet

June 2003

TTSV02622 STS-24 Backplane Transceiver

Registers

(continued)

Register Map

Table 6. Register Map

ADDR

*

Reg. DB7

[6:0] Type

00

01

02

03

04

05

06

SREG

SREG

SREG

CREG

CREG

CREG

PREG

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Reset Comments

Value

(hex)

A0

01

01

00

00

00

Generic

register

block.

FIXED ID MSB

FIXED ID LSB

FIXED REV

SCRATCH PAD

LOCKREG MSB

LOCKREG LSB

—

†

—

†

—

†

—

†

—

†

—

†

FIFO

ALIGNMENT

COMMAND

STS-12

SELECT

GLOBAL

RESET

COMMAND

LVDS LPBK

CONTROL

NA

Device Register Block

08

CREG

—

†

—

†

—

†

Rx TOH

FRAME

AND

Rx TOH

CLOCK

ENABLE

HI-Z

CONTROL

EXT PROT

SW EN

EXT PROT

SW FUNC

00

Device

register block

(Rx).

09

CREG

—

†

—

†

—

†

—

†

—

†

PARALLEL

PORT

OUTPUT

MUX

SELECT

FOR CH1

—

†

SERIAL

PORT

OUTPUT

MUX

SELECT

FOR CH1

0F

0A

0B

0C

CREG

CREG

CREG

—

†

—

†

—

†

—

†

—

†

SCRAMBLER/

DESCREAMBLER

CONTROL

—

†

—

†

I/O

PARALLEL

BUS

PARITY

CONTROL

LINE LPBK

CONTROL

FIFO ALIGNER THRESHOLD VALUE (min)

FIFO ALIGNER THRESHOLD VALUE (max)

NUMBER OF CONSECUTIVE A1/A2 ERRORS TO

GENERATE [3:0]

02

15

60

Device

register block

(Tx).

0D

0E

0F

10

11

12

CREG

CREG

CREG

ISREG

IEREG

IAREG

A1 ERROR INSERT VALUE

A2 ERROR INSERT VALUE

TRANSMITTER B1 ERROR INSERT MASK

00

00

00

†

—

†

—

†

—

†

—

†

—

†

—

†

—

†

—

†

—

†

PER DEVICE

INT

—

†

—

CH 2 INT

CH 1 INT

00

00

Top-level

interrupts.

ENABLE/MASK REGISTER [4:0]

—

†

—

†

—

†

WRITE TO

LOCKED

REGISTER

ERROR FLAG

FRAME

OFFSET

ERROR

FLAG

00

13

IEREG

—

†

—

†

—

†

—

†

—

†

—

†

ENABLE/MASK REGISTER

00

* ADDR values delimited by a comma indicate the address for each of two channels, from channel 1 or 2. For example, the register for Tx

control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control

signals are at address 38.

† Reserved.

Agere Systems Inc.

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