Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Register Descriptions (continued)
Table 7. Register Description (continued)
Address Bit
(hex)
Name
Type
Description
Reset
Value
(hex)
Device Register Blocks
08
0
1
LVDS LPBK
CONTROL
CREG 0 = No loopback.
00
00
1 = LVDS loopback, transmit to receive on.
STS-12 SELECT
CREG This control signal is untracked in the TTSV02622 chip. It
is a scratch bit, and its value has no effect on the
TTSV02622 chip.
[3:2] EXT PROT SW EN CREG EXT PORT
EXT
PROT SW
FUNC
Switching Control Master
00
(bit 3)
SW EN
EXT PROT SW FUNC
(bit 2)
0
—
■ MUX is controlled by software
(1 control bit per MUX).
■ Output buffers are controlled
by software (1 control bit per
channel).
1
1
0
■ MUX on parallel output bus of
CH 1 is controlled by
PROT_SWITCH_A/B pin.
0 = CH 1.
1 = CH 2.
■ Output buffers are controlled
by software (1 control bit per
channel).
1
■ MUX is controlled by software
(1 control bit per MUX).
■ Output buffers on parallel out-
put bus of CH 1 and CH 2 are
controlled by
PROT_SWITCH_A/B pin.
0 = Buffers active.
1 = HI-Z.
4
Rx TOH FRAME
AND Rx TOH CLOCK
ENABLE HI-Z
CREG 0 = High impedance.
00
1 = Enable receive TOH CLK and FP outputs.
CONTROL
[7:5]
Reserved.
Agere Systems Inc.
37
AGERE [ AGERE SYSTEMS ]
