Table 1. Pin Connection Diagram to Achieve Desired CDR Location.
Hard Disk
Connection to PBC Cell
CDR Position (x)
Cell Connection to Cable
ABCDEFG
1234567
xA B C D E F G
0
ABCDEFG
01234567
AxB C D E F G
7
ABCDEFG
01234567
A BxC D E F G
6
ABCDEFG
01234
A B CxD E F G
5
Hard Disk
Connection to PBC Cell
CDR Position (x)
Cell Connection to Cable
ABCDEFG
5670123
A B C DxE F G
4
ABCDEFG
4567012
A B C D ExF G
3
ABCDEFG
3456701
A B C D E FxG
2
ABCDEFG
2345670
A B C D E F Gx
1
x denotes CDR position with respect to hard disks.
FM_NODE[7]+
FM_NODE[6]+
FM_NODE[5]+
TO_NODE[7]+
TO_NODE[6]+
FM_NODE[7]-
FM_NODE[6]-
FM_NODE[5]-
TO_NODE[7]-
TO_NODE[6]-
BYPASS[6]-
BYPASS[7]-
REFCLK
RFCM
FM_NODE[0]_DV
VCC
GND
MODE_VDD
VCCA
GND
CPLL1
CPLL0
FSEL
BYPASS[0]-
FM_NODE[7]_AV
FM_NODE[0]-
FM_NODE[0]+
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BYPASS[5]-
VCCHS
GND
GND
VCC
VCCHS
TO_NODE[5]+
TO_NODE[5]-
VCCHS
TO_NODE[4]+
TO_NODE[4]-
BYPASS[4]-
FM_NODE[4]+
FM_NODE[4]-
GND
FM_NODE[3]+
FM_NODE[3]-
BYPASS[3]-
TO_NODE[3]+
TO_NODE[3]-
VCCHS
Agilent
HDMP-0482
nnnn-nnn Rz.zz
S YYWW
Figure 4. HDMP-0482 Package Layout and Marking, Top View.
nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code
(YY = year, WW = work week); COUNTRY = country of manufacture (on back side).
Table 2. I/O Type Definitions.
I/O Type
I-LVTTL
O-LVTTL
HS_OUT
HS_IN
C
S
Definition
LVTTL Input
LVTTL Output
High Speed Output, LVPECL Compatible
High Speed Input
External circuit node
Power supply or ground
VCC
GND
TO_NODE[0]-
TO_NODE[0]+
VCCHS
TO_NODE[1]-
TO_NODE[1]+
BYPASS[1]-
FM_NODE[1]-
FM_NODE[1]+
VCC
FM_NODE[2]-
FM_NODE[2]+
BYPASS[2]-
TO_NODE[2]-
TO_NODE[2]+
5
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
