Figure 5. Eye Diagram of TO_NODE[1]
±
High Speed Differential Output.
Note: Measurement taken with a 2
7
-1 PRBS input to FM_NODE[0]±.
2
HDMP-0482
+/- FM_NODE[0]
Bias Tee
BYPASS[0]-
BYPASS[1:4]-
N/C
1 KΩ
REFCLK
+/- TO_NODE[0]
1.4V
HP70841B
Pattern Generator
+/- Data
K28.7
Clock
1062.5 MHz
106.25 MHz
2
HP 70311A
Clock Source
1/10
Ch 1/2
106.25 MHz
HP 83480A
Digital
Trigger
Communication
Analyzer
Figure 6. Setup for Measurement of Random Jitter.
2
HDMP-0482
+/- FM_NODE[0]
Bias Tee
BYPASS[0]-
BYPASS[1:4]-
N/C
1 KΩ
REFCLK
+/- TO_NODE[0]
1.4V
HP70841B
Pattern Generator
+/- Data
+K28.5
-K28.5
Clock
1062.5 MHz
106.25 MHz
2
HP 70311A
Clock Source
1/10
Ch 1/2
106.25 MHz
HP 83480A
Digital
Trigger
1/10
Communication
53.125 MHz
Analyzer
Figure 7. Setup for Measurement of Deterministic Jitter.
9
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