Table 3. Pin Definitions for HDMP-0482.
Pin Name
TO_NODE[0]+
TO_NODE[0]-
TO_NODE[1]+
TO_NODE[1]-
TO_NODE[2]+
TO_NODE[2]-
TO_NODE[3]+
TO_NODE[3]-
TO_NODE[4]+
TO_NODE[4]-
TO_NODE[5]+
TO_NODE[5]-
TO_NODE[6]+
TO_NODE[6]-
TO_NODE[7]+
TO_NODE[7]-
FM_NODE[0]+
FM_NODE[0]-
FM_NODE[1]+
FM_NODE[1]-
FM_NODE[2]+
FM_NODE[2]-
FM_NODE[3]+
FM_NODE[3]-
FM_NODE[4]+
FM_NODE[4]-
FM_NODE[5]+
FM_NODE[5]-
FM_NODE[6]+
FM_NODE[6]-
FM_NODE[7]+
FM_NODE[7]-
BYPASS[0]-
BYPASS[1]-
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
BYPASS[5]-
BYPASS[6]-
BYPASS[7]-
REFCLK
CPLL1
CPLL0
FM_NODE[7]_AV
Pin
20
19
23
22
32
31
35
34
44
43
47
46
57
56
60
59
16
15
26
25
29
28
38
37
41
40
51
50
54
53
63
62
13
24
30
36
42
49
55
1
2
10
11
14
Pin Type
HS_OUT
Pin Description
Serial Data Outputs:
High-speed outputs to a hard disk drive or to a cable input.
HS_IN
Serial Data Inputs:
High-speed inputs from a hard disk drive or from a cable output.
I-LVTTL
Bypass Inputs:
For “disk bypassed” mode, connect BYPASS[n]- to GND through a1kΩ resistor.
For “disk in loop” mode, float HIGH.
I-LVTTL
C
O-LVTTL
Reference Clock:
A user-supplied clock reference used for frequency acquisition in
the Clock and Data Recovery (CDR) circuit.
Loop Filter Capacitor:
A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit
must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1
µF.
Amplitude Valid:
Indicates acceptable signal amplitude on the FM_NODE[7]± inputs.
If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1
If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable
If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-),
FM_NODE[7]_AV = 0
Data Valid:
Indicates valid Fibre Channel Data on the FM_NODE[0]± inputs when HIGH. Indicates
either run length violation error or no comma detected when LOW.
Reference Clock Mode:
To configure a one-twentieth-rate reference clock, connect RFCM to
GND through a 1kΩ resistor. To configure a one-tenth-rate reference clock, float RFCM HIGH.
Valid Data Detect Mode:
To allow data valid detection, float MODE_VDD HIGH. To configure chip for
“CDR anywhere” capability, connect MODE_VDD to GND through a 1kΩ resistor.
Frame Select:
To configure single-frame operation of the data valid and amplitude valid
detection circuits, connect FSEL to GND through a 1k resistor. To configure multi-frame (4-frame)
operation of the data valid and amplitude valid detection circuits, float FSEL HIGH.
FM_NODE[0]_DV
RFCM
MODE_VDD
FSEL
4
3
7
12
O-LVTTL
I-LVTTL
I_LVTTL
I_LVTTL
Table 3 is continued on next page.
6
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